Patents by Inventor Natsuki Tsuji
Natsuki Tsuji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10964622Abstract: A cooler (1) has a cooling plate (1a), a cooling fin (1b) provided on a center portion of a lower surface of the cooling plate (1a), and a lower projection (1c) provided on a peripheral portion of the lower surface of the cooling plate (1a). A semiconductor device (3) is provided on an upper surface of the cooling plate (1a). A bus bar (5) is connected to the semiconductor device (3). A cooling mechanism (8) encloses a lower surface and a lateral surface of the cooler (1). An O-ring (9) is provided between a lower surface of the lower projection (1c) and a bottom surface of the cooling mechanism (8). A bolt (10) penetrates a sidewall of the cooling mechanism (8) and screws the cooler (1) to the cooling mechanism (8).Type: GrantFiled: May 24, 2017Date of Patent: March 30, 2021Assignee: Mitsubishi Electric CorporationInventors: Ryoji Murai, Natsuki Tsuji
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Patent number: 10916483Abstract: An object of the present invention is to provide a semiconductor device having a structure in which a resin hardly enters between an insert electrode and a nut at a time of resin sealing. The semiconductor device according to the present invention includes an insert electrode having an insert hole into which a bolt is inserted from outside, a nut which has a screw hole to be screwed with the bolt and is disposed on an inside of the insert electrode so that the screw hole is communicated with the insert hole, at least one semiconductor element being electrically connected to the insert electrode, and a resin sealing the inside of the insert electrode, the nut, and the at least one semiconductor element, wherein a burr is provided on an outer periphery of a direct contact surface of the nut being in direct contact with the insert electrode.Type: GrantFiled: April 23, 2019Date of Patent: February 9, 2021Assignee: Mitsubishi Electric CorporationInventors: Takahiko Murakami, Mitsunori Aiko, Takaaki Shirasawa, Natsuki Tsuji
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Publication number: 20200083141Abstract: A cooler (1) has a cooling plate (1a), a cooling fin (1b) provided on a center portion of a lower surface of the cooling plate (1a), and a lower projection (1c) provided on a peripheral portion of the lower surface of the cooling plate (1a). A semiconductor device (3) is provided on an upper surface of the cooling plate (1a). A bus bar (5) is connected to the semiconductor device (3). A cooling mechanism (8) encloses a lower surface and a lateral surface of the cooler (1). An O-ring (9) is provided between a lower surface of the lower projection (1c) and a bottom surface of the cooling mechanism (8). A bolt (10) penetrates a sidewall of the cooling mechanism (8) and screws the cooler (1) to the cooling mechanism (8).Type: ApplicationFiled: May 24, 2017Publication date: March 12, 2020Applicant: Mitsubishi Electric CorporationInventors: Ryoji MURAI, Natsuki TSUJI
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Patent number: 10510642Abstract: The present invention relates to a semiconductor device module which includes: a semiconductor device including a top electrode and a bottom electrode; a substrate on which the bottom electrode of the semiconductor device is bonded; a heat sink on which the substrate is mounted; a lead electrode through which a main current of the semiconductor device flows; an insulating case disposed to enclose the substrate; and a retainer disposed in a cantilevered manner in the insulating case, the retainer supporting the lead electrode, wherein the lead electrode has one end brazed to the top electrode of the semiconductor device, and another end side inserted into a wall of the insulating case, and the retainer is engaged on the one end of the lead electrode to restrict movement of the lead electrode.Type: GrantFiled: June 3, 2016Date of Patent: December 17, 2019Assignee: Mitsubishi Electric CorporationInventors: Arata Iizuka, Korehide Okamoto, Natsuki Tsuji
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Publication number: 20190252276Abstract: An object of the present invention is to provide a semiconductor device having a structure in which a resin hardly enters between an insert electrode and a nut at a time of resin sealing. The semiconductor device according to the present invention includes an insert electrode having an insert hole into which a bolt is inserted from outside, a nut which has a screw hole to be screwed with the bolt and is disposed on an inside of the insert electrode so that the screw hole is communicated with the insert hole, at least one semiconductor element being electrically connected to the insert electrode, and a resin sealing the inside of the insert electrode, the nut, and the at least one semiconductor element, wherein a burr is provided on an outer periphery of a direct contact surface of the nut being in direct contact with the insert electrode.Type: ApplicationFiled: April 23, 2019Publication date: August 15, 2019Applicant: Mitsubishi Electric CorporationInventors: Takahiko MURAKAMI, Mitsunori AIKO, Takaaki SHIRASAWA, Natsuki TSUJI
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Patent number: 10304748Abstract: An object of the present invention is to provide a semiconductor device having a structure in which a resin hardly enters between an insert electrode and a nut at a time of resin sealing. The semiconductor device according to the present invention includes an insert electrode having an insert hole into which a bolt is inserted from outside, a nut which has a screw hole to be screwed with the bolt and is disposed on an inside of the insert electrode so that the screw hole is communicated with the insert hole, at least one semiconductor element being electrically connected to the insert electrode, and a resin sealing the inside of the insert electrode, the nut, and the at least one semiconductor element, wherein a burr is provided on an outer periphery of a direct contact surface of the nut being in direct contact with the insert electrode.Type: GrantFiled: July 27, 2015Date of Patent: May 28, 2019Assignee: Mitsubishi Electric CorporationInventors: Takahiko Murakami, Mitsunori Aiko, Takaaki Shirasawa, Natsuki Tsuji
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Publication number: 20190131213Abstract: The present invention relates to a semiconductor device module which includes: a semiconductor device including a top electrode and a bottom electrode; a substrate on which the bottom electrode of the semiconductor device is bonded; a heat sink on which the substrate is mounted; a lead electrode through which a main current of the semiconductor device flows; an insulating case disposed to enclose the substrate; and a retainer disposed in a cantilevered manner in the insulating case, the retainer supporting the lead electrode, wherein the lead electrode has one end brazed to the top electrode of the semiconductor device, and another end side inserted into a wall of the insulating case, and the retainer is engaged on the one end of the lead electrode to restrict movement of the lead electrode.Type: ApplicationFiled: June 3, 2016Publication date: May 2, 2019Applicant: Mitsubishi Electric CorporationInventors: Arata IIZUKA, Korehide OKAMOTO, Natsuki TSUJI
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Publication number: 20180068913Abstract: An object of the present invention is to provide a semiconductor device having a structure in which a resin hardly enters between an insert electrode and a nut at a time of resin sealing. The semiconductor device according to the present invention includes an insert electrode having an insert hole into which a bolt is inserted from outside, a nut which has a screw hole to be screwed with the bolt and is disposed on an inside of the insert electrode so that the screw hole is communicated with the insert hole, at least one semiconductor element being electrically connected to the insert electrode, and a resin sealing the inside of the insert electrode, the nut, and the at least one semiconductor element, wherein a burr is provided on an outer periphery of a direct contact surface of the nut being in direct contact with the insert electrode.Type: ApplicationFiled: July 27, 2015Publication date: March 8, 2018Applicant: Mitsubishi Electric CorporationInventors: Takahiko MURAKAMI, Mitsunori AIKO, Takaaki SHIRASAWA, Natsuki TSUJI
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Patent number: 9472538Abstract: Fixing a semiconductor element to a substrate, electrically connecting signal and main terminals to the semiconductor element, a terminal aggregate includes a frame portion, the signal terminal, the main terminal, which has a larger width than the signal terminal, and a dummy terminal, and forming a to-be-encapsulated body in which the substrate, the semiconductor element, and the terminal aggregate are integrated, mounting the to-be-encapsulated body on a lower mold half such that a plurality of blocks formed in the lower mold half are meshed with the signal, main, and dummy terminals with no space left therebetween after the mounting, placing a bottom surface of an upper mold half on top surfaces of the plurality of blocks, and top surfaces of the signal, main, and dummy terminals to form a cavity for the substrate and the semiconductor element, and performing molding by injecting mold resin into the cavity are included.Type: GrantFiled: July 4, 2013Date of Patent: October 18, 2016Assignee: Mitsubishi Electric CorporationInventors: Seiichiro Inokuchi, Mitsunori Aiko, Shintaro Araki, Natsuki Tsuji
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Publication number: 20160079221Abstract: Fixing a semiconductor element to a substrate, electrically connecting signal and main terminals to the semiconductor element, a terminal aggregate includes a frame portion, the signal terminal, the main terminal, which has a larger width than the signal terminal, and a dummy terminal, and forming a to-be-encapsulated body in which the substrate, the semiconductor element, and the terminal aggregate are integrated, mounting the to-be-encapsulated body on a lower mold half such that a plurality of blocks formed in the lower mold half are meshed with the signal, main, and dummy terminals with no space left therebetween after the mounting, placing a bottom surface of an upper mold half on top surfaces of the plurality of blocks, and top surfaces of the signal, main, and dummy terminals to form a cavity for the substrate and the semiconductor element, and performing molding by injecting mold resin into the cavity are included.Type: ApplicationFiled: July 4, 2013Publication date: March 17, 2016Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Seiichiro INOKUCHI, Mitsunori AIKO, Shintaro ARAKI, Natsuki TSUJI
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Patent number: 7777533Abstract: The present invention provides a semiconductor device includes arms formed by two semiconductor elements, a map memory device which stores therein a correlation map between a control value for each of the arms and an optimized dead time to be set for the control value or is capable of storing the same therein, drive control value acquiring means for acquiring a drive control value of each of the arms, and a dead time generating circuit for extracting the optimized dead time corresponding to the drive control value from the correlation map. The time taken until the other of the semiconductor elements is turned on after one thereof has received a command to turn off the same is the optimized dead time extracted by the dead time generating circuit.Type: GrantFiled: May 7, 2008Date of Patent: August 17, 2010Assignee: Mitsubishi Electric CorporationInventors: Noboru Miyamoto, Natsuki Tsuji
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Publication number: 20090096502Abstract: The present invention provides a semiconductor device includes arms formed by two semiconductor elements, a map memory device which stores therein a correlation map between a control value for each of the arms and an optimized dead time to be set for the control value or is capable of storing the same therein, drive control value acquiring means for acquiring a drive control value of each of the arms, and a dead time generating circuit for extracting the optimized dead time corresponding to the drive control value from the correlation map. The time taken until the other of the semiconductor elements is turned on after one thereof has received a command to turn off the same is the optimized dead time extracted by the dead time generating circuit.Type: ApplicationFiled: May 7, 2008Publication date: April 16, 2009Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Noboru MIYAMOTO, Natsuki Tsuji
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Patent number: 7101793Abstract: A method of manufacturing a power module is implemented which allows easy electrical connections between a control board and relay terminals. The diameter of through holes in the control board tapers down from a side of penetration of the relay terminals in a direction of the penetration, and respective one ends of the relay terminals have a smaller diameter than the other portions of the relay terminals. The diameter of the through holes on the side of penetration of the relay terminals is made sufficiently greater than the diameter of the one ends of the relay terminals, so that the relay terminals can easily penetrate the through holes. Further, even if the relay terminals are formed in deviated positions, the one ends of the relay terminals can be guided along the walls of the through holes in the penetration, so that the relay terminals can be adjusted to proper positions.Type: GrantFiled: April 14, 2005Date of Patent: September 5, 2006Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Natsuki Tsuji
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Publication number: 20060139857Abstract: A method of manufacturing a power module is implemented which allows easy electrical connections between a control board and relay terminals. The diameter of through holes in the control board tapers down from a side of penetration of the relay terminals in a direction of the penetration, and respective one ends of the relay terminals have a smaller diameter than the other portions of the relay terminals. The diameter of the through holes on the side of penetration of the relay terminals is made sufficiently greater than the diameter of the one ends of the relay terminals, so that the relay terminals can easily penetrate the through holes. Further, even if the relay terminals are formed in deviated positions, the one ends of the relay terminals can be guided along the walls of the through holes in the penetration, so that the relay terminals can be adjusted to proper positions.Type: ApplicationFiled: April 14, 2005Publication date: June 29, 2006Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventor: Natsuki Tsuji
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Patent number: 6642576Abstract: An IGBT (121) and a diode (131) are joined onto an element arrangement portion (111a) of a first terminal member (111) and an element arrangement portion (112a) of a second terminal member (112) is joined onto the IGBT (121) and the diode (131). Further, an IGBT (122) and a diode (132) are joined onto the element arrangement portion (112a) of the second terminal member (112) and an element arrangement portion (113a) of a third terminal member (113) is joined onto the IGBT (122) and the diode (132). A transfer mold package (141) is so formed as to house the elements (121, 122, 131, 132). External connection portions (111b, 112b, 113b) of the terminal members (111, 112, 113) are drawn out of the package (141). The element arrangement portion(s) (111a, 113a) of the first and/or third terminal member (111, 113) are/is exposed out of the package (141).Type: GrantFiled: December 30, 2002Date of Patent: November 4, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takaaki Shirasawa, Yasuo Koutake, Tsuyoshi Takayama, Natsuki Tsuji