Patents by Inventor Natsuko Ito

Natsuko Ito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8202394
    Abstract: In a method of manufacturing a semiconductor device with plasma generated in a process chamber by impressing radio-frequency power, a level of a radio-frequency power for each step is switched over in response to processing in each step upon applying a plurality of processing steps to a semiconductor substrate while holding the semiconductor substrate, and thereby the plurality of steps are carried out successively.
    Type: Grant
    Filed: June 11, 2002
    Date of Patent: June 19, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Tsuyoshi Moriya, Natsuko Ito, Fumihiko Uesugi
  • Patent number: 8051799
    Abstract: An apparatus includes a housing defining a chamber in which an electric field is generated, and an internal member provided in the chamber. At least one part of the internal member is formed of a dielectric material. A process is executed in the chamber so that a dielectric deposit is formed on the at least one part of the internal member. An m1(d?1/dm1) value of the dielectric material and an m2(d?2/dm2) value of the dielectric deposit are set so that production of particles from the deposit is properly controlled. The term m1 is a mass density of the dielectric material, ?1 is a permittivity of the dielectric material, m2 is a mass density of the dielectric deposit, and ?2 is a permittivity of the dielectric deposit.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: November 8, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Yousuke Itagaki, Natsuko Ito, Fumihiko Uesugi
  • Patent number: 7974067
    Abstract: In a plasma processing apparatus having an electrostatic chuck for holding a semiconductor wafer by an electrostatic adsorption force and a DC power supply for applying an electrostatic adsorption voltage to the electrostatic chuck, abnormal discharge in plasma is suppressed by providing the apparatus with a signal detector that detects a foresee signal that foresees occurrence of abnormal discharge in plasma, and a controller that controls ESC leakage current based upon the foresee signal. If the foresee signal is outside a prescribed range, control is exercised so as to reduce the absolute value of the electrostatic adsorption voltage, thereby suppressing the occurrence of an abnormal discharge.
    Type: Grant
    Filed: September 1, 2006
    Date of Patent: July 5, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Natsuko Ito, Mitsuo Yasaka, Fumihiko Uesugi, Yousuke Itagaki
  • Publication number: 20080233756
    Abstract: In a semiconductor device manufacturing apparatus that processing a substrate by applying a voltage to a gas to create a plasma, positively charged particles are trapped or guided at the instant that the cathode voltage is stopped, by an electrode to which is imparted a negative voltage, so as to prevent particles reaching the substrate.
    Type: Application
    Filed: May 23, 2008
    Publication date: September 25, 2008
    Inventors: Natsuko Ito, Fumihiko Uesugi, Tsuyoshi Moriya
  • Publication number: 20080041306
    Abstract: An apparatus includes a housing defining a chamber in which an electric field is generated, and an internal member provided in the chamber. At least one part of the internal member is formed of a dielectric material. A process is executed in the chamber so that a dielectric deposit is formed on the at least one part of the internal member. An m1(d?1/dm1) value of the dielectric material and ?n m2(d?2/dm2) value of the dielectric deposit are set so that production of particles from the deposit is properly controlled. The term m1 is a mass density of the dielectric material, ?1 is a permittivity of the dielectric material, m2 is a mass density of the dielectric deposit, and ?2 is a permittivity of the dielectric deposit.
    Type: Application
    Filed: June 28, 2007
    Publication date: February 21, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Yousuke ITAGAKI, Natsuko Ito, Fumihiko Uesugi
  • Publication number: 20070058322
    Abstract: In a plasma processing apparatus having an electrostatic chuck for holding a semiconductor wafer by an electrostatic adsorption force and a DC power supply for applying an electrostatic adsorption voltage to the electrostatic chuck, abnormal discharge in plasma is suppressed by providing the apparatus with a signal detector that detects a foresee signal that foresees occurrence of abnormal discharge in plasma, and a controller that controls ESC leakage current based upon the foresee signal. If the foresee signal is outside a prescribed range, control is exercised so as to reduce the absolute value of the electrostatic adsorption voltage, thereby suppressing the occurrence of an abnormal discharge.
    Type: Application
    Filed: September 1, 2006
    Publication date: March 15, 2007
    Inventors: Natsuko Ito, Mitsuo Yasaka, Fumihiko Uesugi, Yousuke Itagaki
  • Publication number: 20060131272
    Abstract: In a semiconductor device manufacturing apparatus that processing a substrate by applying a voltage to a gas to create a plasma, positively charged particles are trapped or guided at the instant that the cathode voltage is stopped, by an electrode to which is imparted a negative voltage, so as to prevent particles reaching the substrate.
    Type: Application
    Filed: February 15, 2006
    Publication date: June 22, 2006
    Inventors: Natsuko Ito, Fumihiko Uesugi, Tsuyoshi Moriya
  • Patent number: 7045465
    Abstract: In a semiconductor device manufacturing apparatus that processing a substrate by applying a voltage to a gas to create a plasma, positively charged particles are trapped or guided at the instant that the cathode voltage is stopped, by an electrode to which is imparted a negative voltage, so as to prevent particles reaching the substrate.
    Type: Grant
    Filed: October 5, 2001
    Date of Patent: May 16, 2006
    Assignee: NEC Electronics Corporation
    Inventors: Natsuko Ito, Fumihiko Uesugi, Tsuyoshi Moriya
  • Patent number: 7006682
    Abstract: There is provided an apparatus for monitoring a size of a particle, including (a) a laser beam source which radiates a laser beam to an area in which particles exist, (b) a photodetector which receives the laser beam having been scattered by the particles, and outputs image data including brightness of pixels, (c) an area detector which detects pixels corresponding to an area on which the scattered laser beam is incident, based on the image data, (d) a maximum brightness detector which detects a maximum brightness among brightness of the pixels detected by the area detector, and (e) a measurement unit which compares the maximum brightness to a predetermined threshold brightness to thereby measure a relative size of the particles.
    Type: Grant
    Filed: September 7, 2000
    Date of Patent: February 28, 2006
    Assignee: NEC Corporation
    Inventors: Tsuyoshi Moriya, Fumihiko Uesugi, Natsuko Ito
  • Patent number: 6737666
    Abstract: A cleaning end point detecting apparatus detects an end point of a cleaning process in which contamination attached to an inner wall of a reaction chamber is removed by introducing a cleaning gas into the chamber to produce a cluster cloud and detached particles. An irradiating unit irradiates a laser beam onto the cluster cloud and the detached particles within the reaction chamber to produce a scattered laser beam. A monitoring unit monitors the scattered laser beam as a two-dimensional image information. A judging unit judges the end point of the cleaning process on the basis of the two-dimensional image information. Preferably, the judging unit judges, as the end point of the cleaning process, a time instant when neither the detached particles nor the cluster cloud are detected on the basis of the two-dimensional image information.
    Type: Grant
    Filed: November 27, 2000
    Date of Patent: May 18, 2004
    Assignees: NEC Electronics Corporation, Tokyo Electron Limited
    Inventors: Natsuko Ito, Tsuyoshi Moriya, Fumihiko Uesugi, Yoshinori Kato, Masaru Aomori, Shuji Moriya, Mitsuhiro Tachibana
  • Publication number: 20030003758
    Abstract: In a method of manufacturing a semiconductor device with plasma generated in a process chamber by impressing radio-frequency power, a level of a radio-frequency power for each step is switched over in response to processing in each step upon applying a plurality of processing steps to a semiconductor substrate while holding the semiconductor substrate, and thereby the plurality of steps are carried out successively.
    Type: Application
    Filed: June 11, 2002
    Publication date: January 2, 2003
    Inventors: Tsuyoshi Moriya, Natsuko Ito, Fumihiko Uesugi
  • Patent number: 6423176
    Abstract: In a semiconductor device manufacturing apparatus that processing a substrate by applying a voltage to a gas to create a plasma, positively charged particles are trapped or guided at the instant that the cathode voltage is stopped, by an electrode to which is imparted a negative voltage, so as to prevent particles reaching the substrate.
    Type: Grant
    Filed: October 10, 2000
    Date of Patent: July 23, 2002
    Assignee: NEC Corporation
    Inventors: Natsuko Ito, Fumihiko Uesugi, Tsuyoshi Moriya
  • Publication number: 20020036343
    Abstract: A semiconductor fabrication device includes a processing chamber in which the interior is substantially sealed. An upper processing electrode and a lower processing electrode are provided inside the processing chamber, and a stage made from a material having high thermal conductivity and on which semiconductor substrate is mounted is provided above the lower processing electrode. In this semiconductor fabrication device, for example, processing gas is introduced into the processing chamber, a radio-frequency voltage is applied between the two electrodes to generate plasma, and a process of etching a deposited film on the semiconductor substrate is carried out. While the process is being carried out, the semiconductor substrate is cooled by causing a cooling medium to flow but without allowing the cooling medium to pass through the processing chamber and thus without causing extraneous particles to occur in the processing chamber.
    Type: Application
    Filed: September 13, 2001
    Publication date: March 28, 2002
    Applicant: NEC CORPORATION
    Inventors: Tsuyoshi Moriya, Natsuko Ito, Fumihiko Uesugi
  • Publication number: 20020037652
    Abstract: In a semiconductor manufacturing apparatus, when an electrostatic chucking voltage for holding a semiconductor substrate to a stage is applied, a deposited film or foreign matter attached to the stage is subjected to electrostatic stress, causing peeling thereof and the generation of particles. To solve this problem, a vacuum suction path is provided having an aperture within a region above the stage immediately below the semiconductor substrate when the semiconductor substrate is fixed thereunto, and the semiconductor substrate is held onto the stage by suction of air from within the suction path, thereby enabling holding of the semiconductor substrate without the application of an electrostatic chucking voltage, making it possible to suppress the generation of particles caused by an electrostatic stress, thereby reducing the number of generated particles.
    Type: Application
    Filed: September 24, 2001
    Publication date: March 28, 2002
    Inventors: Tsuyoshi Moriya, Natsuko Ito, Fumihiko Uesugi
  • Publication number: 20020019141
    Abstract: In a semiconductor device manufacturing apparatus that processing a substrate by applying a voltage to a gas to create a plasma, positively charged particles are trapped or guided at the instant that the cathode voltage is stopped, by an electrode to which is imparted a negative voltage, so as to prevent particles reaching the substrate.
    Type: Application
    Filed: October 5, 2001
    Publication date: February 14, 2002
    Inventors: Natsuko Ito, Fumihiko Uesugi, Tsuyoshi Moriya
  • Patent number: 6346425
    Abstract: A method for processing a substrate includes the steps of determining an allowable margin of process condition such that a substrate is processed without forming particles, selecting a process condition of a substrate for a production process such that the process condition falls in the allowable margin in the production process, and carrying out a processing of the substrate in the production process at the selected process condition, wherein the step of determining the allowable margin includes the steps of introducing an optical beam to an atmosphere in which the substrate is processed in the step of determining the allowable margin, and detecting scattering of the optical beam.
    Type: Grant
    Filed: August 30, 2000
    Date of Patent: February 12, 2002
    Assignees: Tokyo Electron Limited, NEC Corporation
    Inventors: Natsuko Ito, Tsuyoshi Moriya, Fumihiko Uesugi, Shuji Moriya, Masaru Aomori, Yoshinori Kato, Mitsuhiro Tachibana
  • Publication number: 20010041449
    Abstract: A plasma etching apparatus includes a processing chamber for etch-processing a substrate, a lower electrode located within the processing chamber for holding the substrate on an upper surface thereof by an electrostatic attraction, and an upper electrode located to face the lower electrode. A purge gas introducing port is provided at a side wall of the processing chamber at a position which is between the upper electrode and the lower electrode in height and which opposes to the evacuation port in a plan view in such a manner that the lower electrode is positioned between the evacuation port and the purge gas introducing port in the plan view.
    Type: Application
    Filed: March 19, 1999
    Publication date: November 15, 2001
    Inventors: NATSUKO ITO, FUMIHIKO UESUGI, TSUYOSHI MORIYA
  • Patent number: 6306770
    Abstract: A plasma etching apparatus includes a processing chamber for etch-processing a substrate, a lower electrode located within the processing chamber for holding the substrate on an upper surface thereof by an electrostatic attraction, and an upper electrode located to face the lower electrode. A purge gas introducing port is provided at a side wall of the processing chamber at a position which is between the upper electrode and the lower electrode in height and which opposes to the evacuation port in a plan view in such a manner that the lower electrode is positioned between the evacuation port and the purge gas introducing port in the plan view.
    Type: Grant
    Filed: March 19, 1999
    Date of Patent: October 23, 2001
    Assignee: NEC Corporation
    Inventors: Natsuko Ito, Fumihiko Uesugi, Tsuyoshi Moriya
  • Patent number: 6284049
    Abstract: A part of the outer wall of the processing chamber supplied with an active gas for an intended processing forms a protruding section extending out from the outer wall into the air. An incident side window through which laser light is guided is mounted to the protruding portion. A baffle is provided inside the protruding portion for intercepting unnecessary portion of light guided in the processing chamber even if irregularly reflecting light arises, when laser light is guided into the window. An antireflection coating is coated on the air side surface of the window. A purge gas inlet port for blowing out a purge gas along the inside surface of the window is formed in the protruding portion.
    Type: Grant
    Filed: February 15, 2000
    Date of Patent: September 4, 2001
    Assignee: NEC Corporation
    Inventors: Fumihiko Uesugi, Natsuko Ito
  • Patent number: 6184489
    Abstract: In a semiconductor device manufacturing apparatus that processing a substrate by applying a voltage to a gas to create a plasma, positively charged particles are trapped or guided at the instant that the cathode voltage is stopped, by an electrode to which is imparted a negative voltage, so as to prevent particles reaching the substrate.
    Type: Grant
    Filed: April 12, 1999
    Date of Patent: February 6, 2001
    Assignee: NEC Corporation
    Inventors: Natsuko Ito, Fumihiko Uesugi, Tsuyoshi Moriya