Patents by Inventor Natsuo Ajika
Natsuo Ajika has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7573742Abstract: A hot electron (BBHE) is generated close to a drain by tunneling between bands, and bit data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is a drain voltage, a relation of Vg>Vsub>Vs>Vd is satisfied, Vg?Vd is a value of a potential difference required for generating a tunnel current between the bands or higher, and Vsub?Vd is substantially equivalent to a barrier potential of the tunnel insulating film or higher.Type: GrantFiled: October 17, 2006Date of Patent: August 11, 2009Assignee: Genusion, Inc.Inventors: Natsuo Ajika, Shoji Shukuri, Masaaki Mihara, Moriyoshi Nakashima
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Publication number: 20090175083Abstract: The present invention relates to a nonvolatile semiconductor memory, and more specifically relates to a nonvolatile semiconductor memory with increased program throughput. The present invention provides a nonvolatile semiconductor memory device with a plurality of block source lines corresponding to the memory blocks, arranged in parallel to the word lines, a plurality of global source lines arranged in perpendicular to the block source lines; and a plurality of switches for selectively connecting corresponding ones of the block source lines and the global source lines.Type: ApplicationFiled: March 9, 2007Publication date: July 9, 2009Applicant: GENUSION, INC.Inventors: Natsuo Ajika, Shoji Shukuri, Masaaki Mihara, Yoshiki Kawajiri
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Publication number: 20090090961Abstract: A non-volatile semiconductor device includes an n type well formed in a semiconductor substrate having a surface, the surface having a plurality of stripe shaped grooves and a plurality of stripe shaped ribs, a plurality of stripe shaped p type diffusion regions formed in upper parts of each of the plurality of ribs, the plurality of stripe shaped p type diffusion regions being parallel to a longitudinal direction of the ribs, a tunneling insulation film formed on the grooves and the ribs, a charge storage layer formed on the tunneling insulating film, a gate insulation film formed on the charge storage layer, and a plurality of stripe shaped conductors formed on the gate insulating film, the plurality of stripe shaped conductors arranged in a direction intersecting the longitudinal direction of the ribs with a predetermined interval wherein an impurity diffusion structure in the ribs are asymmetric.Type: ApplicationFiled: October 6, 2008Publication date: April 9, 2009Applicant: GENUSION, INC.Inventors: Natsuo Ajika, Shoji Shukuri, Satoshi Shimizu, Taku Ogura
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Patent number: 7515479Abstract: A hot electron (BBHE) is generated close to a drain by tunneling between bands, and bit data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is a drain voltage, a relation of Vg>Vsub>Vs>Vd is satisfied, Vg?Vd is a value of a potential difference required for generating a tunnel current between the bands or higher, and Vsub?Vd is substantially equivalent to a barrier potential of the tunnel insulating film or higher.Type: GrantFiled: November 1, 2005Date of Patent: April 7, 2009Assignee: Genusion, Inc.Inventors: Natsuo Ajika, Shoji Shukuri, Masaaki Mihara, Moriyoshi Nakashima
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Publication number: 20090065922Abstract: A semiconductor chip mounted interposer (60) is configured by executing wire bonding between a semiconductor chip (50) and an interposer (20), in which terminals (21) that connect to terminals (51) of the chip (50) and separate terminals (22) are formed, on the upper face of the interposer (20). A semiconductor chip (30) is mounted to the top face of a package substrate (10), the interposer (60) is adhered to the upper portion of the chip (30), and wire bonding is executed between the terminals (22) and terminals (11?). When configuring a semiconductor device with a plurality of semiconductor chips combined into one package in this manner, KGD (Known-Good-Die) can easily be guaranteed for each semiconductor chip, and semiconductor devices can be fabricated with a high yield of good units. Also, the semiconductor chips can be used as-is, without restricting the position, pitch, signal arrangement, or the like, of their terminals.Type: ApplicationFiled: September 23, 2008Publication date: March 12, 2009Inventors: Moriyoshi NAKASHIMA, Kazuo Kobayashi, Natsuo Ajika
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Publication number: 20080273387Abstract: A hot electron (BBHE) is generated close to a drain by tunneling between bands, and bit data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is a drain voltage, a relation of Vg>Vsub>Vs>Vd is satisfied, Vg?Vd is a value of a potential difference required for generating a tunnel current between the bands or higher, and Vsub?Vd is substantially equivalent to a barrier potential of the tunnel insulating film or higher.Type: ApplicationFiled: November 1, 2005Publication date: November 6, 2008Applicant: GENUSION, INC.Inventors: Natsuo Ajika, Shoji Shukuri, Masaaki Mihara, Moriyoshi Nakashima
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Publication number: 20080265433Abstract: A semiconductor device can be manufactured with a high non-defect ratio, making it possible to easily guarantee the KGD (Known-Good-Die) of semiconductor chips, when configuring one packaged semiconductor device on which a plurality of semiconductor chips is mounted. Utilizing each semiconductor chip is made possible without limits on terminal position, pitch, signal arrangement, and so on. Protrusions provided to a semiconductor chip mounted sealing sub-board are attached to a package substrate. A plurality of semiconductor bare chips is disposed in a space formed between the semiconductor chip mounted sealing sub-board and the package substrate, making wiring possible.Type: ApplicationFiled: June 30, 2008Publication date: October 30, 2008Inventors: Moriyoshi NAKASHIMA, Kazuo Kobayashi, Natsuo Ajika
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Patent number: 7420206Abstract: A semiconductor device can be manufactured with a high non-defect ratio, making it possible to easily guarantee the KGD (Known-Good-Die) of semiconductor chips, when configuring one packaged semiconductor device on which a plurality of semiconductor chips is mounted. Utilizing each semiconductor chip is made possible without limits on terminal position, pitch, signal arrangement, and so on. Protrusions provided to a semiconductor chip mounted sealing sub-board are attached to a package substrate. A plurality of semiconductor bare chips is disposed in a space formed between the semiconductor chip mounted sealing sub-board and the package substrate, making wiring possible.Type: GrantFiled: July 12, 2006Date of Patent: September 2, 2008Assignee: Genusion Inc.Inventors: Moriyoshi Nakashima, Kazuo Kobayashi, Natsuo Ajika
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Publication number: 20080186766Abstract: According to an one aspect of the present invention, it is provided a non-volatile semiconductor memory device comprising: a first N type well; a plurality of P type non-volatile memory cells arranged in matrix and formed in the N type well; a plurality of sub-bit lines, each of the sub-bit lines being connected to drains of the P type non-volatile memory cells in a respective one of columns of the matrix; a first P type well; and a plurality of N type selection transistors, each of the selection transistors selectively connecting a respective one of sub-bit lines to a corresponding one of main bit lines.Type: ApplicationFiled: February 4, 2008Publication date: August 7, 2008Applicant: GENUSION, INC.Inventors: Taku Ogura, Natsuo Ajika
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Publication number: 20080121878Abstract: A semiconductor device can be manufactured with a high non-defect ratio, making it possible to easily guarantee the KGD (Known-Good-Die) of semiconductor chips, when configuring one packaged semiconductor device on which a plurality of semiconductor chips is mounted. Utilizing each semiconductor chip is made possible without limits on terminal position, pitch, signal arrangement, and so on. Protrusions provided to a semiconductor chip mounted sealing sub-board are attached to a package substrate. A plurality of semiconductor bare chips is disposed in a space formed between the semiconductor chip mounted sealing sub-board and the package substrate, making wiring possible.Type: ApplicationFiled: July 12, 2006Publication date: May 29, 2008Inventors: Moriyoshi Nakashima, Kazuo Kobayashi, Natsuo Ajika
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Publication number: 20070230251Abstract: A hot electron (BBHE) is generated close to a drain by tunneling between bands, and it data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is a drain voltage, a relation of Vg>Vsub>Vs>Vd is satisfied, Vg?Vd is a value of a potential difference required for generating a tunnel current between the bands or higher, and Vsub?Vd is substantially equivalent to a barrier potential of the tunnel insulating film or higher.Type: ApplicationFiled: October 17, 2006Publication date: October 4, 2007Applicant: GENUSION, INC.Inventors: Natsuo Ajika, Shoji Shukuri, Masaaki Mihara, Moriyoshi Nakashima
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Publication number: 20070190724Abstract: It is an object to provide a semiconductor device capable of holding multibit information in one memory cell also when scaling for a nonvolatile memory progresses, and a method of manufacturing the semiconductor device. A trench (TRI) is formed in a channel portion of an MONOS transistor. Then, a source side portion and a drain side portion in a silicon nitride film (122) of a gate insulating film (120) which interpose the trench (TR1) are caused to function as first and second electric charge holding portions capable of holding electric charges (CH1) and (CH2). In the case in which the electric charges (CH1) are trapped and the electric charges (CH2) are then trapped, thus, a portion (130a) of a gate electrode (130) in the trench (TR1) functions as a shield. If a fixed potential is given to the gate electrode (130), the second electric charge holding portion is not influenced by an electric field (EF1) induced by the electric charges (CH1) so that the trapping of the electric charges (CH2) is not inhibited.Type: ApplicationFiled: March 23, 2007Publication date: August 16, 2007Applicant: Renesas Technology Corp.Inventors: Yasuyoshi Itoh, Shuuichi Ueno, Haruo Furuta, Natsuo Ajika
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Publication number: 20070132080Abstract: A semiconductor chip mounted interposer (60) is configured by executing wire bonding between a semiconductor chip (50) and an interposer (20), in which terminals (21) that connect to terminals (51) of the chip (50) and separate terminals (22) are formed, on the upper face of the interposer (20). A semiconductor chip (30) is mounted to the top face of a package substrate (10), the interposer (60) is adhered to the upper portion of the chip (30), and wire bonding is executed between the terminals (22) and terminals (11?). When configuring a semiconductor device with a plurality of semiconductor chips combined into one package in this manner, KGD (Known-Good-Die) can easily be guaranteed for each semiconductor chip, and semiconductor devices can be fabricated with a high yield of good units. Also, the semiconductor chips can be used as-is, without restricting the position, pitch, signal arrangement, or the like, of their terminals.Type: ApplicationFiled: December 15, 2003Publication date: June 14, 2007Inventors: Moriyoshi Nakashima, Kazuo Kobayashi, Natsuo Ajika
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Publication number: 20050169050Abstract: It is an object to provide a semiconductor device capable of holding multibit information in one memory cell also when scaling for a nonvolatile memory progresses, and a method of manufacturing the semiconductor device. A trench (TR1) is formed in a channel portion of an MONOS transistor. Then, a source side portion and a drain side portion in a silicon nitride film (122) of a gate insulating film (120) which interpose the trench (TR1) are caused to function as first and second electric charge holding portions capable of holding electric charges (CH1) and (CH2). In the case in which the electric charges (CH1) are trapped and the electric charges (CH2) are then trapped, thus, a portion (130a) of a gate electrode (130) in the trench (TR1) functions as a shield. If a fixed potential is given to the gate electrode (130), the second electric charge holding portion is not influenced by an electric field (EF1) induced by the electric charges (CH1) so that the trapping of the electric charges (CH2) is not inhibited.Type: ApplicationFiled: February 8, 2005Publication date: August 4, 2005Applicant: Renesas Technology Corp.Inventors: Yasuyoshi Itoh, Shuuichi Ueno, Haruo Furuta, Natsuo Ajika
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Patent number: 6867455Abstract: A semiconductor device capable of holding multibit information in one memory cell, and a method of manufacturing the semiconductor device. A trench is formed in a channel portion of an MONOS transistor. Then, a source side portion and a drain side portion in a silicon nitride film of a gate insulating film which interpose the trench are caused to function as first and second electric charge holding portions capable of holding electric charges. In the case in which first electric charges are trapped on the drain side and second electric charges are trapped on the source side, a portion of a gate electrode in the trench functions as a shield. If a fixed potential is given to the gate electrode, the second electric charge holding portion is not influenced by an electric field induced by the first electric charges so that the trapping of the second electric charges is not inhibited.Type: GrantFiled: June 23, 2003Date of Patent: March 15, 2005Assignee: Renesas Technology Corp.Inventors: Yasuyoshi Itoh, Shuuichi Ueno, Haruo Furuta, Natsuo Ajika
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Publication number: 20040026745Abstract: It is an object to provide a semiconductor device capable of holding multibit information in one memory cell also when scaling for a nonvolatile memory progresses, and a method of manufacturing the semiconductor device. A trench (TR1) is formed in a channel portion of an MONOS transistor. Then, a source side portion and a drain side portion in a silicon nitride film (122) of a gate insulating film (120) which interpose the trench (TR1) are caused to function as first and second electric charge holding portions capable of holding electric charges (CH1) and (CH2). In the case in which the electric charges (CH1) are trapped and the electric charges (CH2) are then trapped, thus, a portion (130a) of a gate electrode (130) in the trench (TR1) functions as a shield. If a fixed potential is given to the gate electrode (130), the second electric charge holding portion is not influenced by an electric field (EF1) induced by the electric charges (CH1) so that the trapping of the electric charges (CH2) is not inhibited.Type: ApplicationFiled: June 23, 2003Publication date: February 12, 2004Applicant: RenesasTechnology Corp.Inventors: Yasuyoshi Itoh, Shuuichi Ueno, Haruo Furuta, Natsuo Ajika
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Publication number: 20040008551Abstract: A non-volatile semiconductor memory device usable in relatively wide applications and a method of manufacturing the same are provided. A NOR-type flash memory region (2) including a NOR-type memory cell transistor and a DINOR-type flash memory region (3) including a DINOR-type memory cell transistor are manufactured into a single semiconductor chip (1). A peripheral circuit region (7) including a transistor for a peripheral circuit or the like is manufactured into a region surrounding the NOR-type flash memory region (2) and the DINOR-type flash memory region (3). The peripheral circuit region (7) is shareable between the NOR-type flash memory region (2) and the DINOR-type flash memory region (3) by electrical connection to both of the regions.Type: ApplicationFiled: July 8, 2003Publication date: January 15, 2004Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Tatsuya Shiromoto, Natsuo Ajika, Satoshi Shimizu
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Patent number: 6611459Abstract: A non-volatile semiconductor memory device usable in relatively wide applications and a method of manufacturing the same are provided. A NOR-type flash memory region (2) including a NOR-type memory cell transistor and a DINOR-type flash memory region (3) including a DINOR-type memory cell transistor are manufactured into a single semiconductor chip (1). A peripheral circuit region (7) including a transistor for a peripheral circuit or the like is manufactured into a region surrounding the NOR-type flash memory region (2) and the DINOR-type flash memory region (3). The peripheral circuit region (7) is shareable between the NOR-type flash memory region (2) and the DINOR-type flash memory region (3) by electrical connection to both of the regions.Type: GrantFiled: June 10, 2002Date of Patent: August 26, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tatsuya Shiromoto, Natsuo Ajika, Satoshi Shimizu
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Publication number: 20030128584Abstract: A non-volatile semiconductor memory device usable in relatively wide applications and a method of manufacturing the same are provided. A NOR-type flash memory region (2) including a NOR-type memory cell transistor and a DINOR-type flash memory region (3) including a DINOR-type memory cell transistor are manufactured into a single semiconductor chip (1). A peripheral circuit region (7) including a transistor for a peripheral circuit or the like is manufactured into a region surrounding the NOR-type flash memory region (2) and the DINOR-type flash memory region (3). The peripheral circuit region (7) is shareable between the NOR-type flash memory region (2) and the DINOR-type flash memory region (3) by electrical connection to both of the regions.Type: ApplicationFiled: June 10, 2002Publication date: July 10, 2003Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Tatsuya Shiromoto, Natsuo Ajika, Satoshi Shimizu
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Patent number: 6441426Abstract: In a semiconductor substrate surface, first and second trenches extending in parallel with each other in a bit line direction are provided. An insulation film for trench isolation is filled in the first and second trenches. A floating gate is provided between the first and second trenches on the semiconductor substrate. A sidewall spacer is provided on a sidewall surface, extending in the bit line direction, of the floating gate.Type: GrantFiled: June 16, 1999Date of Patent: August 27, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Atsushi Fukumoto, Natsuo Ajika