Patents by Inventor Natsuo Yamaguchi
Natsuo Yamaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10651277Abstract: In a vertical power MOSFET having a superjunction structure, the withstand voltage of the power MOSFET can be ensured even if the aspect ratios of an n-type column region and a p-type column region are increased so as to vary the impurity concentration of the p-type column region. P-type semiconductor regions PR1 are formed on the sides of an n-type column NC1 adjacent to a p-type column region PC1. In this configuration, the p-type semiconductor region PR1 is formed from the upper end of the n-type column region NC1 to about a half depth of a height from the upper end to the lower end of the side of the n-type column region NC1. This inclines the sides of the overall p-type column region including the p-type semiconductor regions PR1 and the p-type column region PC1.Type: GrantFiled: March 11, 2019Date of Patent: May 12, 2020Assignee: Renesas Electronics CorporationInventors: Yuya Abiko, Natsuo Yamaguchi, Satoshi Eguchi
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Patent number: 10355122Abstract: Properties of a semiconductor device are improved. A semiconductor device having a superjunction structure, in which p-type column regions and n-type column regions are periodically arranged, is configured as follows. Each n-type column region has a vertical section including an n-type epitaxial layer located between trenches and a tapered embedded n-type epitaxial film disposed on a side face of the trench. Each p-type column region includes an embedded p-type epitaxial film disposed within the trench. The tapered embedded n-type epitaxial film is thus provided on the sidewall of the trench in which the p-type column region is to be disposed, thereby the p-type column region is allowed to have an inverted trapezoidal shape, leading to an increase in margin for a variation in concentration of a p-type impurity in the p-type column region. On resistance can be reduced by lateral diffusion of an n-type impurity (for example, As).Type: GrantFiled: June 30, 2017Date of Patent: July 16, 2019Assignee: Renesas Electronics CorporationInventors: Yuya Abiko, Satoshi Eguchi, Shigeaki Saito, Daisuke Taniguchi, Natsuo Yamaguchi
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Publication number: 20190207001Abstract: In a vertical power MOSFET having a superjunction structure, the withstand voltage of the power MOSFET can be ensured even if the aspect ratios of an n-type column region and a p-type column region are increased so as to vary the impurity concentration of the p-type column region. P-type semiconductor regions PR1 are formed on the sides of an n-type column NC1 adjacent to a p-type column region PC1. In this configuration, the p-type semiconductor region PR1 is formed from the upper end of the n-type column region NC1 to about a half depth of a height from the upper end to the lower end of the side of the n-type column region NC1. This inclines the sides of the overall p-type column region including the p-type semiconductor regions PR1 and the p-type column region PC1.Type: ApplicationFiled: March 11, 2019Publication date: July 4, 2019Inventors: Yuya ABIKO, Natsuo YAMAGUCHI, Satoshi EGUCHI
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Patent number: 10204987Abstract: In a semiconductor device including a super junction structure that p-type columns and n-type columns are periodically arranged, a depth of a p-type column region in a cell region that a semiconductor element is formed is made shallower than a depth of a p-type column region in an intermediate region which surrounds the cell region. Thereby, a breakdown voltage of the cell region becomes lower than a breakdown voltage of the intermediate region. An avalanche breakdown phenomenon is caused to occur preferentially in the cell region in which even when an avalanche current is generated, the current is dispersed and smoothly flows. Thereby, it is possible to avoid local current constriction and breakage incidental thereto and consequently it becomes possible to improve avalanche resistance (an avalanche current amount with which a semiconductor device comes to be broken).Type: GrantFiled: January 11, 2018Date of Patent: February 12, 2019Assignee: Renesas Electronics CorporationInventors: Yuya Abiko, Satoshi Eguchi, Akio Ichimura, Natsuo Yamaguchi, Tetsuya Iida
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Publication number: 20180286952Abstract: In a vertical power MOSFET having a superjunction structure, the withstand voltage of the power MOSFET can be ensured even if the aspect ratios of an n-type column region and a p-type column region are increased so as to vary the impurity concentration of the p-type column region. P-type semiconductor regions PR1 are formed on the sides of an n-type column NC1 adjacent to a p-type column region PC1. In this configuration, the p-type semiconductor region PR1 is formed from the upper end of the n-type column region NC1 to about a half depth of a height from the upper end to the lower end of the side of the n-type column region NC1. This inclines the sides of the overall p-type column region including the p-type semiconductor regions PR1 and the p-type column region PC1.Type: ApplicationFiled: February 5, 2018Publication date: October 4, 2018Inventors: Yuya ABIKO, Natsuo YAMAGUCHI, Satoshi EGUCHI
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Publication number: 20180158910Abstract: In a semiconductor device including a super junction structure that p-type columns and n-type columns are periodically arranged, a depth of a p-type column region in a cell region that a semiconductor element is formed is made shallower than a depth of a p-type column region in an intermediate region which surrounds the cell region. Thereby, a breakdown voltage of the cell region becomes lower than a breakdown voltage of the intermediate region. An avalanche breakdown phenomenon is caused to occur preferentially in the cell region in which even when an avalanche current is generated, the current is dispersed and smoothly flows. Thereby, it is possible to avoid local current constriction and breakage incidental thereto and consequently it becomes possible to improve avalanche resistance (an avalanche current amount with which a semiconductor device comes to be broken).Type: ApplicationFiled: January 11, 2018Publication date: June 7, 2018Inventors: Yuya ABIKO, Satoshi EGUCHI, Akio ICHIMURA, Natsuo YAMAGUCHI, Tetsuya IIDA
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Publication number: 20180076313Abstract: Properties of a semiconductor device are improved. A semiconductor device having a superjunction structure, in which p-type column regions and n-type column regions are periodically arranged, is configured as follows. Each n-type column region has a vertical section including an n-type epitaxial layer located between trenches and a tapered embedded n-type epitaxial film disposed on a side face of the trench. Each p-type column region includes an embedded p-type epitaxial film disposed within the trench. The tapered embedded n-type epitaxial film is thus provided on the sidewall of the trench in which the p-type column region is to be disposed, thereby the p-type column region is allowed to have an inverted trapezoidal shape, leading to an increase in margin for a variation in concentration of a p-type impurity in the p-type column region. On resistance can be reduced by lateral diffusion of an n-type impurity (for example, As).Type: ApplicationFiled: June 30, 2017Publication date: March 15, 2018Inventors: Yuya ABIKO, Satoshi EGUCHI, Shigeaki SAITO, Daisuke TANIGUCHI, Natsuo YAMAGUCHI
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Patent number: 9905644Abstract: In a semiconductor device including a super junction structure that p-type columns and n-type columns are periodically arranged, a depth of a p-type column region in a cell region that a semiconductor element is formed is made shallower than a depth of a p-type column region in an intermediate region which surrounds the cell region. Thereby, a breakdown voltage of the cell region becomes lower than a breakdown voltage of the intermediate region. An avalanche breakdown phenomenon is caused to occur preferentially in the cell region in which even when an avalanche current is generated, the current is dispersed and smoothly flows. Thereby, it is possible to avoid local current constriction and breakage incidental thereto and consequently it becomes possible to improve avalanche resistance (an avalanche current amount with which a semiconductor device comes to be broken).Type: GrantFiled: December 11, 2015Date of Patent: February 27, 2018Assignee: Renesas Electronics CorporationInventors: Yuya Abiko, Satoshi Eguchi, Akio Ichimura, Natsuo Yamaguchi, Tetsuya Iida
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Publication number: 20160204192Abstract: In a semiconductor device including a super junction structure that p-type columns and n-type columns are periodically arranged, a depth of a p-type column region in a cell region that a semiconductor element is formed is made shallower than a depth of a p-type column region in an intermediate region which surrounds the cell region. Thereby, a breakdown voltage of the cell region becomes lower than a breakdown voltage of the intermediate region. An avalanche breakdown phenomenon is caused to occur preferentially in the cell region in which even when an avalanche current is generated, the current is dispersed and smoothly flows. Thereby, it is possible to avoid local current constriction and breakage incidental thereto and consequently it becomes possible to improve avalanche resistance (an avalanche current amount with which a semiconductor device comes to be broken).Type: ApplicationFiled: December 11, 2015Publication date: July 14, 2016Inventors: Yuya ABIKO, Satoshi EGUCHI, Akio ICHIMURA, Natsuo YAMAGUCHI, Tetsuya IIDA
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Patent number: 8035169Abstract: A technique that makes it possible to suppress a crystal defect produced in an active area and thereby reduce the fraction defective of semiconductor devices is provided. A first embodiment relates to the planar configuration of SRAM. One of the features of the first embodiment is as illustrated in FIG. 4. That is, on the precondition that the active areas in n-channel MISFET formation regions are all configured in the isolated structure: the width of the terminal sections is made larger than the width of the central parts of the active areas. For example, the terminal sections are formed in an L shape.Type: GrantFiled: October 31, 2008Date of Patent: October 11, 2011Assignee: Renesas Electronics CorporationInventors: Hiroshi Ishida, Atsushi Maeda, Minoru Abiko, Takehiko Kijima, Takashi Takeuchi, Shoji Yoshida, Natsuo Yamaguchi, Yasuhiro Kimura, Tetsuya Uchida, Norio Ishitsuka
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Publication number: 20100140711Abstract: Generation of dislocation and increase of diffusion resistance at edge portions of source/drain regions in a CMIS are prevented. When source/drain regions in a CMIS are formed, argon is implanted to a P-well layer as a dislocation-suppressing element and nitrogen is implanted to an N-well layer as a dislocation-suppressing element before an ion implantation of impurities to a silicon substrate. In this manner, by separately implanting dislocation-suppressing elements suitable for each of the P-well layer and the N-well layer as well as suppressing the generation of dislocation, increase of diffusion resistance can be suppressed, yield can be improved, and the reliability of devices can be increased.Type: ApplicationFiled: December 1, 2009Publication date: June 10, 2010Applicant: RENESAS TECHNOLOGY CORP.Inventors: Norio ISHITSUKA, Hiroyuki OHTA, Yasuhiro KIMURA, Natsuo YAMAGUCHI, Takashi TAKEUCHI, Shoji YOSHIDA
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Publication number: 20090134467Abstract: A technique that makes it possible to suppress a crystal defect produced in an active area and thereby reduce the fraction defective of semiconductor devices is provided. A first embodiment relates to the planar configuration of SRAM. One of the features of the first embodiment is as illustrated in FIG. 4. That is, on the precondition that the active areas in n-channel MISFET formation regions are all configured in the isolated structure: the width of the terminal sections is made larger than the width of the central parts of the active areas. For example, the terminal sections are formed in an L shape.Type: ApplicationFiled: October 31, 2008Publication date: May 28, 2009Inventors: Hiroshi ISHIDA, Atsushi Maeda, Minoru Abiko, Takehiko Kijima, Takashi Takeuchi, Shoji Yoshida, Natsuo Yamaguchi, Yasuhiro Kimura, Tetsuya Uchida, Norio Ishitsuka