Patents by Inventor Naushad Variam
Naushad Variam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11462546Abstract: A method may include providing a substrate, the substrate comprising a substrate base and a patterning stack, disposed on the substrate base. The substrate may include first linear structures in the patterning stack, the first linear structures being elongated along a first direction; and second linear structures in the patterning stack, the second linear structures being elongated along a second direction, the second direction forming a non-zero angle with respect to the first direction. The method may also include selectively forming a set of sidewall spacers on one set of sidewalls of the second linear structures.Type: GrantFiled: January 31, 2020Date of Patent: October 4, 2022Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Sony Varghese, Naushad Variam
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Publication number: 20200168612Abstract: A method may include providing a substrate, the substrate comprising a substrate base and a patterning stack, disposed on the substrate base. The substrate may include first linear structures in the patterning stack, the first linear structures being elongated along a first direction; and second linear structures in the patterning stack, the second linear structures being elongated along a second direction, the second direction forming a non-zero angle with respect to the first direction. The method may also include selectively forming a set of sidewall spacers on one set of sidewalls of the second linear structures.Type: ApplicationFiled: January 31, 2020Publication date: May 28, 2020Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Sony Varghese, Naushad Variam
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Patent number: 10607999Abstract: A method may include providing a substrate, the substrate comprising a substrate base and a patterning stack, disposed on the substrate base. The substrate may include first linear structures in the patterning stack, the first linear structures being elongated along a first direction; and second linear structures in the patterning stack, the second linear structures being elongated along a second direction, the second direction forming a non-zero angle with respect to the first direction. The method may also include selectively forming a set of sidewall spacers on one set of sidewalls of the second linear structures.Type: GrantFiled: November 3, 2017Date of Patent: March 31, 2020Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Sony Varghese, Naushad Variam
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Publication number: 20190139964Abstract: A method may include providing a substrate, the substrate comprising a substrate base and a patterning stack, disposed on the substrate base. The substrate may include first linear structures in the patterning stack, the first linear structures being elongated along a first direction; and second linear structures in the patterning stack, the second linear structures being elongated along a second direction, the second direction forming a non-zero angle with respect to the first direction. The method may also include selectively forming a set of sidewall spacers on one set of sidewalls of the second linear structures.Type: ApplicationFiled: November 3, 2017Publication date: May 9, 2019Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Sony Varghese, Naushad Variam
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Patent number: 9679776Abstract: A method for the selective implantation of a workpiece is disclosed. In place of conventional photoresist, a two layer structure is used. The first layer, referred to as the protective layer, is applied directly to the workpiece and protects the workpiece from harmful etching processes. Additionally, the protective layer has limited ability to stop ions from impacting the workpiece. The second layer, referred to as the blocking layer, which is formed on a portion of the protective layer, is used to block ions from impacting the underlying workpiece. Advantageously, the blocking layer may be selectively etched without affecting the protective layer. Additionally, the protective layer can be removed without affecting the underlying workpiece. Through the use of this two layer technique, high temperature selective implants may be performed on a variety of different semiconductor devices.Type: GrantFiled: July 23, 2015Date of Patent: June 13, 2017Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Andrew M. Waite, Naushad Variam
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Publication number: 20170025277Abstract: A method for the selective implantation of a workpiece is disclosed. In place of conventional photoresist, a two layer structure is used. The first layer, referred to as the protective layer, is applied directly to the workpiece and protects the workpiece from harmful etching processes. Additionally, the protective layer has limited ability to stop ions from impacting the workpiece. The second layer, referred to as the blocking layer, which is formed on a portion of the protective layer, is used to block ions from impacting the underlying workpiece. Advantageously, the blocking layer may be selectively etched without affecting the protective layer. Additionally, the protective layer can be removed without affecting the underlying workpiece. Through the use of this two layer technique, high temperature selective implants may be performed on a variety of different semiconductor devices.Type: ApplicationFiled: July 23, 2015Publication date: January 26, 2017Inventors: Andrew M. Waite, Naushad Variam
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Patent number: 7544959Abstract: Methods and apparatus that introduce, within the ion implant chamber or an isolated chamber in communication therewith, the capability to remove contaminants and oxide surface layers on a wafer surface prior to ion implantation, are disclosed. The mechanisms for removal of contaminants include conducting: a low energy plasma etch, heating the wafer and application of ultraviolet illumination, either in combination or individually. As a result, implantation can occur immediately after the cleaning/preparation process without the contamination potential of exposure of the wafer to an external environment. The preparation allows for the removal of surface contaminants, such as water vapor, organic materials and surface oxides.Type: GrantFiled: April 8, 2008Date of Patent: June 9, 2009Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Steven R. Walther, Sandeep Mehta, Naushad Variam, Ukyo Jeong
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Publication number: 20080185537Abstract: Methods and apparatus that introduce, within the ion implant chamber or an isolated chamber in communication therewith, the capability to remove contaminants and oxide surface layers on a wafer surface prior to ion implantation, are disclosed. The mechanisms for removal of contaminants include conducting: a low energy plasma etch, heating the wafer and application of ultraviolet illumination, either in combination or individually. As a result, implantation can occur immediately after the cleaning/preparation process without the contamination potential of exposure of the wafer to an external environment. The preparation allows for the removal of surface contaminants, such as water vapor, organic materials and surface oxides.Type: ApplicationFiled: April 8, 2008Publication date: August 7, 2008Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Steve Walther, Sandeep Mehta, Naushad Variam, Ukyo Jeong
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Publication number: 20070123012Abstract: A method for fabricating a semiconductor-based device includes providing a substrate including a semiconductor layer, forming a gate dielectric layer on the semiconductor layer, forming a plasma including deuterium, plasma implanting deuterium from the plasma into the substrate, and annealing the substrate to promote passivation of the interface between the dielectric layer and the semiconductor layer.Type: ApplicationFiled: November 29, 2005Publication date: May 31, 2007Inventors: Steven Walther, Ukyo Jeong, Sandeep Mehta, Naushad Variam
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Publication number: 20070069157Abstract: Methods and apparatus for plasma ion implantation with improved dopant profiles are provided. A plasma ion implantation system includes a process chamber, a plasma source to generate a plasma in the process chamber, a platen to hold the substrate in the process chamber and a pulse source to generate implant pulses to accelerate ions from the plasma into the substrate. In one aspect, the pulse source generates implant pulses having pulse widths that are sufficiently long to limit plasma ion implantation during a transient period at the start of each implant pulse to a small fraction of the total implanted dose. In another aspect, ions are generated in a region of the process chamber near a reference potential, such as ground, and are accelerated from the region of plasma generation to the platen. Plasma generation may be enabled after the start of each implant pulse and may be disabled before the end of each implant pulse.Type: ApplicationFiled: September 28, 2005Publication date: March 29, 2007Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Sandeep Mehta, Steven Walther, Naushad Variam, Ukyo Jeong
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Publication number: 20070048984Abstract: A system, method and program product for adjusting metal work function by ion implantation is disclosed. The invention determines the work function of the metal and determines a desired work function threshold for the metal. The desired work function threshold may be a range and is usually based on the work function of the substrate. An ion implanter system is then used to implant ions to at least a portion of the metal. The ion implantation is usually a high-energy ion stream including a material that is calculated to modify the work function of the metal. The ion implanter system continues to transmit the ion stream into the metal until the work function of the metal meets the desired work function threshold.Type: ApplicationFiled: August 31, 2005Publication date: March 1, 2007Inventors: Steven Walther, Ukyo Jeong, Sandeep Mehta, Naushad Variam
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Publication number: 20060219952Abstract: Plasma ion implantation apparatus includes a process chamber, a platen located in the process chamber for supporting a substrate, a dopant source including a solid dopant element and a vaporizer to vaporize dopant material from the solid dopant element, a plasma source to produce a plasma containing ions of the dopant material, and an implant pulse source to apply implant pulses to the platen for accelerating the ions of the dopant material from the plasma into the substrate.Type: ApplicationFiled: March 9, 2005Publication date: October 5, 2006Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Sandeep Mehta, Steven Walther, Naushad Variam
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Publication number: 20060205192Abstract: A method for fabricating a semiconductor-based device includes disposing a substrate in a process chamber of a process tool, plasma implanting a dopant species from a plasma into a portion of the substrate in the process chamber, and plasma depositing a diffusion barrier on the implanted portion of the substrate prior to removing the at least one substrate from the process tool. The diffusion barrier can be deposited in the same chamber as that used for dopant implantation or a different chamber of the process tool.Type: ApplicationFiled: March 9, 2005Publication date: September 14, 2006Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Steven Walther, Sandeep Mehta, Ukyo Jeong, Naushad Variam
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Publication number: 20060040499Abstract: Methods and apparatus that introduce, within the ion implant chamber or an isolated chamber in communication therewith, the capability to remove contaminants and oxide surface layers on a wafer surface prior to ion implantation, are disclosed. The mechanisms for removal of contaminants include conducting: a low energy plasma etch, heating the wafer and application of ultraviolet illumination, either in combination or individually. As a result, implantation can occur immediately after the cleaning/preparation process without the contamination potential of exposure of the wafer to an external environment. The preparation allows for the removal of surface contaminants, such as water vapor, organic materials and surface oxides.Type: ApplicationFiled: August 20, 2004Publication date: February 23, 2006Inventors: Steve Walther, Sandeep Mehta, Naushad Variam, Ukyo Jeong