Abstract: A memory controller includes a first arbiter for selecting memory commands for dispatch to a memory over a first channel, a second arbiter for selecting memory commands for dispatch to the memory over a second channel, and a test circuit. The test circuit generates a respective testing sequence of read commands and write commands for each of the first channel and second channel, and causes the testing sequences to be transmitted over the first and second channels at least partially overlapping in time without selection by the first or second arbiters.

Abstract: Disclosed are various embodiments for delegated evaluation of a decision tree. A client device receives an expression and a plurality of responses from a second computing device, the expression providing an evaluation of a user input and each of the plurality of responses representing a potential response for the first computing device to provide to the user input. The client device then evaluates the user input with the expression received from the second computing device to determine a user intent. The client device then selects a response to the user intent from the plurality of responses and renders the response within a user interface.

Abstract: Disclosed are various embodiments for delegated evaluation of a decision tree. A client device receives an expression and a plurality of responses from a second computing device, the expression providing an evaluation of a user input and each of the plurality of responses representing a potential response for the first computing device to provide to the user input. The client device then evaluates the user input with the expression received from the second computing device to determine a user intent. The client device then selects a response to the user intent from the plurality of responses and renders the response within a user interface.