Patents by Inventor Naveen Jain

Naveen Jain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230231723
    Abstract: Implementations generally relate to fan emoji identifications. In some implementations, a method includes generating a primary emoji identifier (ID), wherein the primary emoji ID is digitally signed with a primary private encryption key, and wherein the primary emoji ID is associated with a primary user. The method further includes generating a splitter emoji, wherein the splitter emoji demarcates the primary emoji ID. The method further includes generating a secondary emoji identifier (ID), wherein secondary emoji ID is associated with a secondary user. The method further includes concatenating the primary emoji ID, the splitter emoji, and the secondary emoji ID, wherein the combination of the primary emoji ID and the secondary emoji ID provides an attestation of an affinity of the secondary user to the primary user.
    Type: Application
    Filed: January 18, 2022
    Publication date: July 20, 2023
    Inventors: Naveen JAIN, Riccardo SPAGNI
  • Patent number: 8638532
    Abstract: A system and method for controlling an over current protection trip point for a voltage regulator includes an input for receiving a monitored operating parameter of the voltage regulator. Control logic responsive to this input generates a digital current control signal. A digital to analog controller converts the digital current control signal to an analog current control signal and this analog current control signal is used for controlling a current source for generating a current that establishes the over current protection trip point of the voltage regulator.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: January 28, 2014
    Assignee: Intersil Americas LLC
    Inventors: Gustavo James Mehas, Atul Wokhlu, Naveen Jain, Xiaole Chen
  • Patent number: 8593970
    Abstract: In one embodiment, a processor-readable medium can store code representing instructions that when executed by a processor cause the processor to receive a value representing a congestion level of a receive queue and a value representing a state of a transmit queue. At least a portion of the transmit queue can be defined by a plurality of packets addressed to the receive queue. A rate value for the transmit queue can be defined based on the value representing the congestion level of the receive queue and the value representing the state of the transmit queue. The processor-readable medium can store code representing instructions that when executed by the processor cause the processor to define a suspension time value for the transmit queue based on the value representing the congestion level of the receive queue and the value representing the state of the transmit queue.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: November 26, 2013
    Assignee: Juniper Networks, Inc.
    Inventors: Avanindra Godbole, Arghajit Basu, Jean-Marc Frailong, Abhijeet Sampatrao Jadav, Naveen Jain, Pradeep Sindhu
  • Patent number: 8578240
    Abstract: A communication device may include a cyclic redundancy check (CRC) calculator. The CRC calculator may determine a packet remainder of a packet based on a data path width associated with the communication device; append zeros to the packet remainder to generate an appended packet remainder equal in size to the data path width; compute a first CRC value for the appended packet; reverse bits of the computed first CRC value to obtain a reversed CRC value; multiply the bit reversed CRC value with a value based on a reciprocal CRC polynomial to generate a multiplication product; compute a second CRC value for the generated multiplication product based on the reciprocal CRC polynomial; and reverse bits of the second CRC value to generate a CRC for the packet.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: November 5, 2013
    Assignee: Juniper Networks, Inc.
    Inventors: Ravi Pathakota, Abhijeet Sampatrao Jadhav, Sai Kishore, Naveen Jain
  • Publication number: 20120269065
    Abstract: In one embodiment, a processor-readable medium can store code representing instructions that when executed by a processor cause the processor to receive a value representing a congestion level of a receive queue and a value representing a state of a transmit queue. At least a portion of the transmit queue can be defined by a plurality of packets addressed to the receive queue. A rate value for the transmit queue can be defined based on the value representing the congestion level of the receive queue and the value representing the state of the transmit queue. The processor-readable medium can store code representing instructions that when executed by the processor cause the processor to define a suspension time value for the transmit queue based on the value representing the congestion level of the receive queue and the value representing the state of the transmit queue.
    Type: Application
    Filed: July 3, 2012
    Publication date: October 25, 2012
    Applicant: Juniper Networks, Inc.
    Inventors: Avanindra GODBOLE, Arghajit BASU, Jean-Marc FRAILONG, Abhijeet Sampatrao JADAV, Naveen JAIN, Pradeep SINDHU
  • Publication number: 20120257312
    Abstract: A system and method for controlling an over current protection trip point for a voltage regulator includes an input for receiving a monitored operating parameter of the voltage regulator. Control logic responsive to this input generates a digital current control signal. A digital to analog controller converts the digital current control signal to an analog current control signal and this analog current control signal is used for controlling a current source for generating a current that establishes the over current protection trip point of the voltage regulator.
    Type: Application
    Filed: June 25, 2012
    Publication date: October 11, 2012
    Applicant: INTERSIL AMERICAS LLC
    Inventors: GUSTAVO JAMES MEHAS, ATUL WOKHLU, NAVEEN JAIN, XIAOLE CHEN
  • Patent number: 8255252
    Abstract: A system and method for facilitating consistent management of a repeatable contract audit, resolution and recovery process is disclosed. A methodology that tightly defines the contract audit, resolution and recovery events enables an audit team to evaluate supplier performance against a contract, ascertain the existing health of a contract, and identify opportunities to improve and/or re-engineer a contracting process. The method begins with a meeting with a client, followed by a meeting with the supplier, and progresses to a process review, data collection, and a data analysis, which results in recommendations that are presented to the supplier based on the findings of the audit team. The audit team then works with the supplier to resolve any issues identified by the data analysis.
    Type: Grant
    Filed: January 10, 2008
    Date of Patent: August 28, 2012
    Assignee: American Express Travel Related Services Company, Inc.
    Inventors: Arpit Chug, Naveen Jain, Rakesh Kanda, Chetan Lohani, Shachindra Pandey
  • Patent number: 8233256
    Abstract: A system and method for controlling an over current protection trip point for a voltage regulator includes an input for receiving a monitored operating parameter of the voltage regulator. Control logic responsive to this input generates a digital current control signal. A digital to analog controller converts the digital current control signal to an analog current control signal and this analog current control signal is used for controlling a current source for generating a current that establishes the over current protection trip point of the voltage regulator.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: July 31, 2012
    Assignee: Intersil Americas Inc
    Inventors: Gustavo James Mehas, Atul Wokhlu, Naveen Jain, Xiaole Chen
  • Patent number: 8213308
    Abstract: In one embodiment, a processor-readable medium can store code representing instructions that when executed by a processor cause the processor to receive a value representing a congestion level of a receive queue and a value representing a state of a transmit queue. At least a portion of the transmit queue can be defined by a plurality of packets addressed to the receive queue. A rate value for the transmit queue can be defined based on the value representing the congestion level of the receive queue and the value representing the state of the transmit queue. The processor-readable medium can store code representing instructions that when executed by the processor cause the processor to define a suspension time value for the transmit queue based on the value representing the congestion level of the receive queue and the value representing the state of the transmit queue.
    Type: Grant
    Filed: September 11, 2009
    Date of Patent: July 3, 2012
    Assignee: Juniper Networks, Inc.
    Inventors: Avanindra Godbole, Arghajit Basu, Jean-Marc Frailong, Abhijeet Sampatrao Jadav, Naveen Jain, Pradeep Sindhu
  • Patent number: 8120336
    Abstract: A synchronous regulator includes a controller coupled to receive a reference signal and a feedback signal from the regulator and being operable to provide a pulse width modulation (PWM) signal at its output. The regulator includes at least one gate driver coupled to receive the PWM signal and includes a synchronous output switch having a phase node therebetween controlled by the gate driver, and also including regulator input current measurement circuitry. The regulator input current measurement circuitry includes a circuit that provides a signal representative of at least one phase node timing parameter. A sensing circuit is operable to sense inductor or output current provided by the regulator. A calculation circuit is coupled to receive the signal representative of the phase node timing parameters and the inductor or output current and is operable to determine the input current from the phase node timing parameters and the inductor or output current.
    Type: Grant
    Filed: September 3, 2010
    Date of Patent: February 21, 2012
    Assignee: Intersil Americas Inc.
    Inventors: Gustavo James Mehas, Naveen Jain, Jayant Vivrekar, Michael Jason Houston
  • Publication number: 20110160274
    Abstract: The present invention provides a formulation of fenofibrate with enhanced oral bioavailability, simplicity of design and manufacture and absence of food effect. The formulation comprises fenofibrate dissolved in a lipophilic surfactant, with a hydrophilic surfactant optionally added. The formulation can be effectively used in the management and treatment of conditions such as hypertriglyceridemia, hypercholesterolemia and mixed dyslipidemia, and can also be effective at lower doses as compared to commercially available products. The invention additionally relates to the process of manufacture of the formulation and to dosage forms comprising the same.
    Type: Application
    Filed: June 26, 2009
    Publication date: June 30, 2011
    Applicant: PANACEA BIOTEC LIMITED
    Inventors: Rajesh Jain, Sarabjit Singh, Naveen Jain, Shivanand Puthli
  • Publication number: 20100327825
    Abstract: A synchronous regulator includes a controller coupled to receive a reference signal and a feedback signal from the regulator operable to provide a pulse width modulation (PWM) signal at its output. The regulator includes at least one gate driver coupled to receive the PWM signal, and a synchronous output switch having a phase node there between controlled by the gate driver, and regulator input current measurement circuitry. The regulator input current measurement circuitry comprises a circuit operable for providing a signal representative of at least one phase node timing parameter, a sensing circuit operable for sensing inductor or output current provided by the regulator, and a calculation circuit coupled to receive the signal representative of the phase node timing parameters and the inductor or output current and is operable to determine the input current.
    Type: Application
    Filed: September 3, 2010
    Publication date: December 30, 2010
    Applicant: INTERSIL AMERICAS INC.
    Inventors: GUSTAVO JAMES MEHAS, NAVEEN JAIN, JAYANT VIVREKAR, MICHAEL JASON HOUSTON
  • Patent number: 7791324
    Abstract: A synchronous regulator includes a controller coupled to receive a reference signal and a feedback signal from the regulator operable to provide a pulse width modulation (PWM) signal at its output. The regulator includes at least one gate driver coupled to receive the PWM signal, and a synchronous output switch having a phase node there between controlled by the gate driver, and regulator input current measurement circuitry. The regulator input current measurement circuitry comprises a circuit operable for providing a signal representative of at least one phase node timing parameter, a sensing circuit operable for sensing inductor or output current provided by the regulator, and a calculation circuit coupled to receive the signal representative of the phase node timing parameters and the inductor or output current and is operable to determine the input current.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: September 7, 2010
    Assignee: Intersil Americas Inc.
    Inventors: Gustavo James Mehas, Naveen Jain, Jayant Vivrekar, Michael Jason Houston
  • Publication number: 20100061390
    Abstract: In one embodiment, a processor-readable medium can store code representing instructions that when executed by a processor cause the processor to receive a value representing a congestion level of a receive queue and a value representing a state of a transmit queue. At least a portion of the transmit queue can be defined by a plurality of packets addressed to the receive queue. A rate value for the transmit queue can be defined based on the value representing the congestion level of the receive queue and the value representing the state of the transmit queue. The processor-readable medium can store code representing instructions that when executed by the processor cause the processor to define a suspension time value for the transmit queue based on the value representing the congestion level of the receive queue and the value representing the state of the transmit queue.
    Type: Application
    Filed: September 11, 2009
    Publication date: March 11, 2010
    Inventors: Avanindra GODBOLE, Arghajit Basu, Jean-Marc Frailong, Abhijeet Sampatrao Jadav, Naveen Jain, Pradeep Sindhu
  • Publication number: 20090182606
    Abstract: A system and method for facilitating consistent management of a repeatable contract audit, resolution and recovery process is disclosed. A methodology that tightly defines the contract audit, resolution and recovery events enables an audit team to evaluate supplier performance against a contract, ascertain the existing health of a contract, and identify opportunities to improve and/or re-engineer a contracting process. The method begins with a meeting with a client, followed by a meeting with the supplier, and progresses to a process review, data collection, and a data analysis, which results in recommendations that are presented to the supplier based on the findings of the audit team. The audit team then works with the supplier to resolve any issues identified by the data analysis.
    Type: Application
    Filed: January 10, 2008
    Publication date: July 16, 2009
    Applicant: American Express Travel Related Services Company, Inc.
    Inventors: Arpit Chug, Naveen Jain, Rakesh Kanda, Chetan Lohani, Shachindra Pandey
  • Publication number: 20090177534
    Abstract: A computer system and computer program product are provided that enable a supervisor to input performance evaluations for members of the supervisor's group. The supervisor is presented with an electronic evaluation form that includes evaluation items that are answered by the supervisor selecting one of a plurality of options. The evaluation form evaluates parameter, sub-parameters, skill types and skill levels as established during maintenance. Each evaluation item is categorized by at least a parameter, sub-parameter, skill type, or skill level. Answers to the evaluation items inputted by the supervisor for each of the members of the group are used to produce a graphical evaluation result based on the answers inputted by the supervisor. Consolidation of several evaluations, from the same supervisor or from several, can also be done.
    Type: Application
    Filed: January 7, 2008
    Publication date: July 9, 2009
    Applicant: American Express Travel Related Services Co., Inc.
    Inventors: AMIT ARORA, Jyoti Rai, Naveen Jain, Vaibhav Sharma, Ruchika Arun, Shino Joseph, Amit Goel
  • Publication number: 20080297957
    Abstract: A system and method for controlling an over current protection trip point for a voltage regulator includes an input for receiving a monitored operating parameter of the voltage regulator. Control logic responsive to this input generates a digital current control signal. A digital to analog controller converts the digital current control signal to an analog current control signal and this analog current control signal is used for controlling a current source for generating a current that establishes the over current protection trip point of the voltage regulator.
    Type: Application
    Filed: February 15, 2008
    Publication date: December 4, 2008
    Applicant: INTERSIL AMERICAS INC.
    Inventors: GUSTAVO JAMES MEHAS, ATUL WOKHLU, NAVEEN JAIN, XIAOLE CHEN
  • Publication number: 20080278123
    Abstract: A synchronous regulator includes a controller coupled to receive a reference signal and a feedback signal from the regulator operable to provide a pulse width modulation (PWM) signal at its output. The regulator includes at least one gate driver coupled to receive the PWM signal, and a synchronous output switch having a phase node there between controlled by the gate driver, and regulator input current measurement circuitry. The regulator input current measurement circuitry comprises a circuit operable for providing a signal representative of at least one phase node timing parameter, a sensing circuit operable for sensing inductor or output current provided by the regulator, and a calculation circuit coupled to receive the signal representative of the phase node timing parameters and the inductor or output current and is operable to determine the input current.
    Type: Application
    Filed: March 31, 2008
    Publication date: November 13, 2008
    Applicant: Intersil Americas Inc.
    Inventors: Gustavo James Mehas, Naveen Jain, Jayant Vivrekar, Jason Houston
  • Publication number: 20070067429
    Abstract: A system and method for dissemination of digital content comprising an integrated content delivery system is established that allows content providers to bid for delivery of their content based on stored, preferential, contextual and or situational data. The system preferably includes a client application that can access stored, preferential, contextual and/or situational data from its origin or the user, communicate the data to a central processing server over a network, and accept content over a network for the user. The central processing server takes into account the market for content directly related to the data communicated by the client application including the amount content providers are willing to pay per transmission.
    Type: Application
    Filed: May 17, 2006
    Publication date: March 22, 2007
    Inventors: Naveen Jain, Shon Sherwood
  • Publication number: 20060248021
    Abstract: Public records are used to help in the detection and prevention of fraud as well as to verify a consumer. Public records are accessed in real-time and then used to determine if a consumer is who they claim to be or is a fraudster. Questions are generated using the public records based on an initial fraud score and a verification level associated with the entity requesting the fraud and verification services. Based on the response to the questions, the fraud score is updated and a confidence level is returned to the requestor to determine whether the user is legitimate or a fraudster. The questions may be presented online or offline. The verification can be different for every merchant.
    Type: Application
    Filed: November 22, 2005
    Publication date: November 2, 2006
    Applicant: Intelius
    Inventors: Naveen Jain, John Arnold, Kevin Marcus, Niraj Shah