Abstract: Apparatus and methods are disclosed, including transistors, semiconductor devices and systems. Example semiconductor devices and methods include isolation trenches between transistors that include a floating liner. Floating liner examples enable trench widths that scale smaller than trenches that do not include floating liners. This allows increases in device density without sacrificing electronic properties of devise shown.

Abstract: An electronic device comprises a stack comprising tiers of alternating conductive structures and insulative structures, and pillars vertically extending through the stack. The pillars comprise a tunnel dielectric material, a channel material, and an insulative material substantially surrounded by the channel material. The electronic device comprises a memory material horizontally adjacent to the conductive structures without being horizontally adjacent to the insulative structures. Related memory devices, systems, and methods of forming the electronic devices are also described.

Abstract: A variety of applications can include apparatus having a transistor comprising a modified channel region to address sub-surface leakage issues of the transistor. A dielectric region can be structured to extend from a channel structure of the transistor downward into the substrate for the transistor, with the dielectric region disposed between the source of the transistor and the drain of the transistor to reduce leakage current paths between the source and the drain. The dielectric region can be structured with only dielectric material or with crystalline semiconductor material surrounded by dielectric material.

Abstract: Some embodiments include an assembly having channel-material-structures, and having memory cells along the channel-material-structures. The memory cells include charge-storage-material. Linear-conductive-structures are vertically offset from the channel-material-structures and are electrically coupled with the channel-material-structures. Intervening regions are between the linear-conductive-structures. Conductive-shield-structures are within the intervening regions. The conductive-shield-structures are electrically coupled with a reference-voltage-source.

Abstract: An apparatus includes lightly doped drain regions vertically extending into a semiconductor substrate. A channel region is horizontally interposed between the lightly doped drain regions, and source/drain regions vertically extend into the lightly doped drain regions. Breakdown-enhancement implant intrusion regions are within the lightly doped drain regions and are horizontally interposed between the channel region and the source/drain regions. The breakdown enhancement implant regions have a different chemical species than the lightly doped drain regions and have upper boundaries vertically underlying upper boundaries of the lightly doped drain regions. The apparatus also has a gate structure vertically overlying the channel regions and it is horizontally interposed between the breakdown-enhancement implant regions. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

Abstract: A method of forming a microelectronic device comprises forming a stack structure comprising vertically alternating insulating structures and conductive structures arranged in tiers. Each of the tiers individually comprises one of the insulating structures and one of the conductive structures. A sacrificial material is formed over the stack structure and pillar structures are formed to extend vertically through the stack structure and the sacrificial material. The method comprises forming conductive plug structures within upper portions of the pillar structures, forming slots extending vertically through the stack structure and the sacrificial material, at least partially removing the sacrificial material to form openings horizontally interposed between the conductive plug structures, and forming a low-K dielectric material within the openings. Microelectronic devices, memory devices, and electronic systems are also described.

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses.

Abstract: A method of forming a microelectronic device comprises forming a stack structure comprising vertically alternating insulating structures and conductive structures arranged in tiers. Each of the tiers individually comprises one of the insulating structures and one of the conductive structures. A sacrificial material is formed over the stack structure and pillar structures are formed to extend vertically through the stack structure and the sacrificial material. The method comprises forming conductive plug structures within upper portions of the pillar structures, forming slots extending vertically through the stack structure and the sacrificial material, at least partially removing the sacrificial material to form openings horizontally interposed between the conductive plug structures, and forming a low-K dielectric material within the openings. Microelectronic devices, memory devices, and electronic systems are also described.

Abstract: A method used in forming a memory array comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory-cell strings extend through the insulative and conductive tiers. Conductive vias are formed above and individually electrically coupled to individual of the channel-material strings. Insulating material is laterally-between immediately-adjacent of the conductive vias. At least some of the insulating material is vertically removed to form an upwardly-open void-space that is circumferentially about multiple of the conductive vias. Insulative material is formed laterally-between the immediately-adjacent conductive vias to form a covered void-space from the upwardly-open void-space. Digitlines are formed above that are individually electrically coupled to a plurality of individual of the conductive vias there-below. Other embodiments, including structure independent of method, are disclosed.

Abstract: An electronic device comprising multilevel bitlines comprising first bitlines and second bitlines. The first bitlines and the second bitlines are positioned at different levels. Pillar contacts are electrically connected to the first bitlines and to the second bitlines. Level 1 contacts are electrically connected to the first bitlines and level 2 contacts are electrically connected to the second bitlines. A liner is between the first bitlines and the level 2 contacts. Each bitline of the first bitlines is electrically connected to a single pillar contact in a subblock adjacent to the level 1 contacts and each bitline of the second bitlines is electrically connected to a single pillar contact adjacent to the level 2 contacts. Methods of forming an electronic device and related systems are also disclosed.

Abstract: An electronic device comprising multilevel bitlines, pillar contacts, level 1 contacts, and level 2 contacts. The multilevel bitlines comprise first bitlines and second bitlines, with the first bitlines and second bitlines positioned at different levels. The pillar contacts are electrically connected to the first bitlines and to the second bitlines, the level 1 contacts are electrically connected to the first bitlines, and the level 2 contacts are electrically connected to the second bitlines. Each bitline of the first bitlines is electrically connected to a single pillar contact adjacent to the level 1 contacts and each bitline of the second bitlines is electrically connected to a single pillar contact adjacent to the level 2 contacts. Additional electronic devices are disclosed, as are methods of forming an electronic device and related systems.

Abstract: A method of forming an apparatus includes forming pillar structures extending vertically through a first isolation material, forming conductive lines operatively coupled to the pillar structures, forming dielectric structures overlying the conductive lines, and forming air gaps between neighboring conductive lines. The air gaps are laterally adjacent to the conductive lines with a portion of the air gaps extending above a plane of an upper surface of the laterally adjacent conductive lines and a portion of the air gaps extending below a plane of a lower surface of the laterally adjacent conductive lines. Apparatuses, memory devices, methods of forming a memory device, and electronic systems are also disclosed.

Abstract: Systems, apparatuses, and methods related to semiconductor structure formation are described. An example apparatus includes a first trench and a second trench formed in a semiconductor substrate material, where the first and second trenches are adjacent and separated by the semiconductor substrate material. The apparatus includes a metallic material formed to a first height in the first trench that is less than, relative to the semiconductor substrate material, a second height of the metallic material formed in the second trench and a polysilicon material formed over the metallic material in the first trench to a first depth greater than, relative to the semiconductor substrate material, a second depth of the polysilicon material formed over the metallic material in the second trench. The greater first depth of the polysilicon material formed in the first trench reduces transfer of charge by way of the metallic material in the first trench.

Abstract: A method of forming an apparatus includes forming pillar structures extending vertically through a first isolation material, forming conductive lines operatively coupled to the pillar structures, forming dielectric structures overlying the conductive lines, and forming air gaps between neighboring conductive lines. The air gaps are laterally adjacent to the conductive lines with a portion of the air gaps extending above a plane of an upper surface of the laterally adjacent conductive lines and a portion of the air gaps extending below a plane of a lower surface of the laterally adjacent conductive lines. Apparatuses, memory devices, methods of forming a memory device, and electronic systems are also disclosed.

Abstract: A microelectronic device includes a stack structure comprising a vertically alternating sequence of insulative and conductive structures arranged in tiers. At least one pillar, comprising a channel material, extends through the stack structure. A source region, below the stack structure, comprises a doped material with vertical extensions that protrude to an interface with the channel material at an elevation proximate at least one source-side GIDL region. Slit structures extend through the stack structure to divide the structure into blocks of pillar arrays. A series of spaced, discrete pedestal structures are included along a base of the slit structures. Forming the microelectronic device structure may include forming a lateral opening through cell materials of the pillar, vertically recessing the channel material, and laterally recessing other material(s) of the pillar before forming the doped material in the broadened recesses.

Abstract: Some embodiments include an integrated assembly having a channel-material-pillar extending vertically through a stack of alternating conductive levels and insulative levels. The channel-material-pillar includes a first semiconductor material. A second semiconductor material is directly against an upper region of the channel-material-pillar. The second semiconductor material has a higher dopant concentration than the first semiconductor material and joins to the first semiconductor along an abrupt interfacial region such that there is little to no mixing of dopant from the second semiconductor material into the first semiconductor material. Some embodiments include methods of forming integrated assemblies.

Abstract: A method of forming a microelectronic device comprises forming a stack structure comprising vertically alternating insulating structures and conductive structures arranged in tiers. Each of the tiers individually comprises one of the insulating structures and one of the conductive structures. A sacrificial material is formed over the stack structure and pillar structures are formed to extend vertically through the stack structure and the sacrificial material. The method comprises forming conductive plug structures within upper portions of the pillar structures, forming slots extending vertically through the stack structure and the sacrificial material, at least partially removing the sacrificial material to form openings horizontally interposed between the conductive plug structures, and forming a low-K dielectric material within the openings. Microelectronic devices, memory devices, and electronic systems are also described.

Abstract: Some embodiments include an assembly having channel-material-structures, and having memory cells along the channel-material-structures. The memory cells include charge-storage-material. Linear-conductive-structures are vertically offset from the channel-material-structures and are electrically coupled with the channel-material-structures. Intervening regions are between the linear-conductive-structures. Conductive-shield-structures are within the intervening regions. The conductive-shield-structures are electrically coupled with a reference-voltage-source.

Abstract: Some embodiments include an assembly having channel-material-structures, and having memory cells along the channel-material-structures. The memory cells include charge-storage-material. Linear-conductive-structures are vertically offset from the channel-material-structures and are electrically coupled with the channel-material-structures. Intervening regions are between the linear-conductive-structures. Conductive-shield-structures are within the intervening regions. The conductive-shield-structures are electrically coupled with a reference-voltage-source.

Abstract: Memory devices can be structured in a three-dimensional arrangement using a circuit under array (CUA) architecture. The memory array of such a memory device can include memory cells disposed in vertically arranged tiers. With the memory array extending over a substrate, the CUA region under the memory array can include control circuitry for the memory array. A space adjacent the memory array and disposed above the CUA region can include a dielectric material and conductive structures, with the conductive structures extending vertically in the dielectric material and alongside the memory array. The conductive structures separated by the dielectric material can be used as a capacitor coupled between nodes with the nodes configured to provide different voltages. This capacitor can be coupled to a circuit or a connection node below the level of the memory array.