Abstract: An apparatus includes a plurality of transceiver circuits, each comprising one or more phase shifter circuits. The phase shifter circuits may be configured to make a phase change by switching at least one of a capacitance value and an inductance value in response to a control signal. A characteristic impedance and the phase of each phase shifter circuit are correlated such that after the phase change, a value of the characteristic impedance is maintained at a predefined value.

Abstract: An apparatus includes an amplifier circuit including a first transistor and a second transistor. The first transistor may include a gate having a gate oxide with a first thickness and a first gate length. The second transistor may include a gate having a gate oxide with a second thickness and a second gate length. The first transistor and the second transistor may be connected in a cascode configuration and the second thickness and the second gate length are greater than the first thickness and the first gate length, respectively.

Abstract: An apparatus includes a transceiver circuit, a series capacitor, and a shunt switch. The transceiver circuit may comprise a transmit chain including an output matching network and a receive chain including an input matching network. An output of the output matching network may be connected directly to an input/output of the transceiver circuit. The series capacitor may be connected between an input of the input matching network and the output of the output matching network. The shunt switch may be connected between the input of the input matching network and a circuit ground potential of the transceiver circuit.

Abstract: An apparatus includes a plurality of transceiver circuits, each comprising one or more phase shifter circuits. The phase shifter circuits may be configured to make a phase change by switching at least one of a capacitance value and an inductance value in response to a control signal. A characteristic impedance and the phase of each phase shifter circuit are correlated such that after the phase change, a value of the characteristic impedance is maintained at a predefined value.

Abstract: An apparatus includes a transceiver circuit, a series capacitor, and a shunt switch. The transceiver circuit may comprise a transmit chain including an output matching network and a receive chain including an input matching network. An output of the output matching network may be connected directly to an input/output of the transceiver circuit. The series capacitor may be connected between an input of the input matching network and the output of the output matching network. The shunt switch may be connected between the input of the input matching network and a circuit ground potential of the transceiver circuit.

Abstract: An apparatus includes a first circuit and a plurality of second circuits. The first circuit may be configured to generate a pair of quadrature signals from a radio-frequency signal. The second circuits may each comprise a plurality of cascode amplifiers. The cascode amplifiers may be connected in parallel. The cascode amplifiers may be configured to generate a plurality of intermediate signals by modulating the quadrature signals in response to a first control signal and a second control signal. The first control signal generally switches a contribution of the cascode amplifiers in the generation of the intermediate signal. The second control signal may adjusts a total current passing through all of the cascode amplifiers.

Abstract: An apparatus includes a phased array antenna panel and a plurality of beam former circuits. The phased array antenna panel generally comprises a plurality of antenna elements. The plurality of beam former circuits are each mounted on the phased array antenna panel adjacent to a number of the antenna elements. Each beam former circuit has one or more ports directly coupled to each of the adjacent antenna elements. Each beam former circuit may be configured to generate a plurality of radio-frequency output signals at the ports while in a transmit mode and receive a plurality of radio-frequency input signals at the ports while in a receive mode. Each beam former circuit generally implements a hard-wired address.

Abstract: An apparatus includes a plurality of conductive layers and a plurality of traces configured to carry a plurality of signals through a change of direction. The traces may be routed parallel to each other in a first trace segment in a first of the conductive layers toward the change of direction. The traces may be routed parallel to each other in a second trace segment in a second of the conductive layers in the change of direction. One of the traces in a third trace segment in the first conductive layer may cross over another of the traces in the second trace segment in the second conductive layer in the change of direction. The traces may be routed parallel to each other in the third trace segment in the first conductive layer away from the change of direction.

Abstract: An apparatus includes a switching circuit and a plurality of registers. The switching circuit may be configured to generate a sequence of pulses in a plurality of control signals in response to a plurality of cycles of an enable signal. The registers may be hardwired as a plurality of subsets. Each of the subsets of the registers may be configured to (a) buffer a plurality of setting values received from a memory and (b) present the setting values from the registers to a plurality of transceiver circuits while a corresponding one of the control signals is in an active state. The transceiver circuits may be updated with the setting values from the registers within a predetermined time.

Abstract: An apparatus includes an impedance matching network, a first switch circuit, and a second switch circuit. The impedance matching network generally comprises a first port, a second port, and a third port. The first switch circuit may be coupled between the first port and a circuit ground potential. The second switch circuit may be coupled between the second port and the circuit ground potential. The impedance matching network generally provides a first impedance value for the first port and for the third port when the second port is connected to the circuit ground potential. The impedance matching network generally provides a second impedance value for the second port and for the third port when the first port is connected to the circuit ground potential. The first impedance value and the second impedance value are asymmetrical.

Abstract: An apparatus comprises an input port, an output port, and a resonant receive switch circuit. The resonant receive switch circuit may be coupled between the input port and the output port. The resonant receive switch circuit may comprise a switch and an input matching circuit. When the switch is in a non-conducting state, a signal at the input port is passed to the output port. When the switch is in a conducting state, the signal at the input port is prevented from reaching the output port.

Abstract: An apparatus includes a plurality of conductive layers and a plurality of traces configured to carry a plurality of signals through a change of direction. The traces may be routed parallel to each other in a first trace segment in a first of the conductive layers toward the change of direction. The traces may be routed parallel to each other in a second trace segment in a second of the conductive layers in the change of direction. One of the traces in a third trace segment in the first conductive layer may cross over another of the traces in the second trace segment in the second conductive layer in the change of direction. The traces may be routed parallel to each other in the third trace segment in the first conductive layer away from the change of direction.

Abstract: An apparatus includes a phased array antenna panel and a plurality of beam former circuits. The phased array antenna panel generally comprises a plurality of antenna elements. The plurality of beam former circuits are each mounted on the phased array antenna panel adjacent to a number of the antenna elements. Each beam former circuit has one or more ports directly coupled to each of the adjacent antenna elements. Each beam former circuit may be configured to generate a plurality of radio-frequency output signals at the ports while in a transmit mode and receive a plurality of radio-frequency input signals at the ports while in a receive mode. Each beam former circuit generally implements a hard-wired address.

Abstract: An apparatus includes a first circuit and a plurality of second circuits. The first circuit may be configured to generate a pair of quadrature signals from a radio-frequency signal. The second circuits may each comprise a plurality of cascode amplifiers. The cascode amplifiers may be connected in parallel. The cascode amplifiers may be configured to generate a plurality of intermediate signals by modulating the quadrature signals in response to a first control signal and a second control signal. The first control signal generally switches a contribution of the cascode amplifiers in the generation of the intermediate signal. The second control signal may adjusts a total current passing through all of the cascode amplifiers.

Abstract: An apparatus includes a switching circuit and a plurality of registers. The switching circuit may be configured to generate a sequence of pulses in a plurality of control signals in response to a plurality of cycles of an enable signal. The registers may be hardwired as a plurality of subsets. Each of the subsets of the registers may be configured to (a) buffer a plurality of setting values received from a memory and (b) present the setting values from the registers to a plurality of transceiver circuits while a corresponding one of the control signals is in an active state. The transceiver circuits may be updated with the setting values from the registers within a predetermined time.

Abstract: An apparatus includes an impedance matching network, a first switch circuit, and a second switch circuit. The impedance matching network generally comprises a first port, a second port, and a third port. The first switch circuit may be coupled between the first port and a circuit ground potential. The second switch circuit may be coupled between the second port and the circuit ground potential. The impedance matching network generally provides a first impedance value for the first port and for the third port when the second port is connected to the circuit ground potential. The impedance matching network generally provides a second impedance value for the second port and for the third port when the first port is connected to the circuit ground potential. The first impedance value and the second impedance value are asymmetrical.

Abstract: An apparatus includes an input port, an output port, a common port, a first impedance matching network, a second impedance matching network, a first switch circuit, and a second switch circuit. The first impedance matching network may be coupled between the input port and the common port. The second impedance matching network may be coupled between the common port and the output port. The first switch circuit may be coupled between the input port and a circuit ground potential. The second switch circuit may be coupled between the output port and the circuit ground potential. The first and the second impedance matching networks are asymmetrical.

Abstract: An apparatus includes a switching circuit and a plurality of registers. The switching circuit may be configured to generate a plurality of control signals in response to an enable signal. One control signal at a time may be active while the enable signal is in a transfer state. The registers may be configured to (i) buffer a plurality of setting values received from a memory and (ii) present the setting values from a subset of the registers to a plurality of transceiver circuits while a corresponding control signal is active. The setting values may include a plurality of phase values and a plurality of gain values used in the transceiver circuits to steer a radio frequency beam. Each transceiver channel may update the setting values from the registers within a predetermined time after a corresponding control signal becomes active.

Abstract: A system and method integrates signal filters in a multiband transceiver. A preferred embodiment comprises an amplifier with a first tunable capacitor coupled to a signal input and a tunable filter. The tunable filter comprises an input stage with a first pair of inductors arranged in a dipole configuration and a second tunable capacitor coupled in parallel to the first pair of inductors and an output stage inductively coupled to the input stage, the output stage includes a second pair of inductors also arranged in a dipole configuration and a third tunable capacitor coupled in parallel to the second pair of inductors. The inductors are realized using bond wire or any other high Q material. The first tunable capacitor, the second tunable capacitor, and the third tunable capacitor can be tuned using a master-slave tuning configuration to adjust the operating frequency of the amplifier and the tunable filter to enable frequency band compatibility with multiple communications protocols.

Abstract: An apparatus for amplifying a signal is provided. The apparatus includes a carrier transistor, a peaking transistor, a controller, and a power supply switching unit, wherein the controller controls the power supply switching unit to switch between two or more power supplies and wherein the power supply switching unit provides power from one of the two or more power supplies to the peaking transistor.