Abstract: Methods and structure are disclosed for improved processing of fast path I/O requests in a storage controller utilizing version information embedded in the fast path I/O requests. The version information allows the storage controller to determine if the mapping information utilized by the host system in generating a fast path I/O request specifies the mapping information utilized by the storage controller. The controller comprises a fast path I/O request processing circuit tightly coupled with host system drivers for fast processing of requests directed to storage devices of a logical volume. The controller also comprises a logical volume I/O processing software stack for processing I/O requests from a host system directed to a logical volume. If the mapping information utilized by the host does not match the mapping information utilized by the storage controller, fast path I/O requests are transferred to the I/O request processing stack for subsequent processing.

Abstract: A method is disclosed for updating parity information in a RAID 6 system wherein only one parity block is read during each write operation. Both parity blocks may be updated from the new data, the data being overwritten and either of the old blocks of parity information. A method for load balancing in a RAID 6 system using this method is also disclosed.

Abstract: A method is disclosed for updating parity information in a RAID 6 system wherein only one parity block is read during each write operation. Both parity blocks may be updated from the new data, the data being overwritten and either of the old blocks of parity information. A method for load balancing in a RAID 6 system using this method is also disclosed.

Abstract: A system and method for performing a mirror set based error handling during a consistency check operation on a RAID 1E disk array is disclosed. In one embodiment, in a method for performing a mirror set based medium error handling during a consistency check (CC) operation on a RAID 1E disk array, a read operation is performed on a current row. The RAID 1E disk array is formed using mirror sets having rows, where each mirror set includes a pair of disks, and the rows include at least one block in each of the pair of disks. A list of all medium errors found in the current row is formed. The medium errors found in the current row are grouped on mirror set basis and the medium errors that do not have a corresponding medium error in substantially same block in other disk in a mirror set are recovered.

Abstract: A system and method for performing a consistency check operation on a degraded RAID 1E disk array is disclosed. In one embodiment, in a method for performing a consistency check on a degraded RAID 1E disk array, a read request is sent to a first row in all mirror sets having no missing disks. Then, an exclusive—OR (XOR) operation is performed on the first row in all the mirror sets having no missing disks for determining data consistency between a pair of disks in the mirror set. Further, data on a mirrored disk in all the mirror sets having no missing disks is updated based on the outcome of the performed XOR operation.

Abstract: A method for creating an output vector Z(n-1:0) from a first vector X(n-1:0) and a second vector Y(n-1:0). The second vector Y(n-1:0) is a complement of the first vector X(n-1:0). The method subdivides X into a lower-order subvector XL(m-1:0) and a higher-order subvector XH(n-1:m). If a first 1 exists in position k in XL, then Z(k) is set to 0 and all other bits in Z(m-1:0) are set to 1. If a first 1 does not exist in XL, then all bits in Z(m-1:0) are set to 1. The method also determines if a 1 exists in XL. If a 1 exists in XL, then Z(n-1:m) is masked.

Abstract: A microprocessor with a circuit that selects at least one instruction from a stream of N successive instruction bytes. The circuit includes a first pointing unit that indicates a position of a first byte of an instruction of the stream of N successive instruction bytes. The circuit also includes a second pointing unit that stores a vector having a length N which indicates a position of a last byte of the instruction in the stream. The circuit further includes a first alignment unit coupled to the first and the second pointing units, the first alignment unit aligns the vector at a position indicating the first byte of an instruction. The circuit includes a first and a second length detecting units that receive the aligned vector in parallel. The first and second length detecting units simultaneously determine the length of a current instruction and the length of a next instruction, respectively, of the stream of N successive instruction bytes.

Abstract: An input/output buffer for computer circuitry including a P type transistor device responsive to data signals for selectively furnishing voltage from a first source of potential at a buffer input/output terminal, a first predriver circuit for furnishing data signals from a source to the P type transistor device, the first predriver circuit including circuitry for slowing the application of data signals to the P type transistor device when the buffer input/output terminal is at a high level, a N type transistor device responsive to data signals for selectively furnishing voltage from a second source of potential at the buffer output terminal, a second predriver circuit for furnishing data signals from the source to the N type transistor device, and circuitry for slowing the receipt of data signals at the first predriver circuit.