Abstract: Disclosed herein is a system. The system includes a memory and a processor. The memory stores processor executable instructions for a recognition engine. The processor is coupled to the memory. The processor executes the processor executable to cause the system to define a plurality of baseline entities to be identified from documents in a workflow and digitize the one or documents to generate corresponding document object models. The recognition engine further causes the system to train a model by using as inputs the corresponding document object models and tagged files and determine, using the model, plurality of target entities from target documents.

Abstract: An integrated clock gate (ICG) includes an OR-AND-INVERT gate to receive a first enable and a second enable; a first inverter coupled to the output of the OR-AND-INVERT; a first NAND gate coupled to the output of the first inverter; a second NAND gate coupled to the output of the OR-AND-INVERT; and a second inverter to provide a clock which is gated based on logic values of the first enable and/or the second enable, wherein an output of the second inverter is received as input by the OR-AND-INVERT-gate. The ICG circuit reduces capacitance of input clk pin, which translates to lower switching power when clock is gated and reduction in dynamic power of clock network, since buffers in clock tree driving the ICG cells can be downsized. The ICG cell has the smallest transistor count (and area) when compared to existing ICG cell topologies.