Patents by Inventor NAVEEN MIRIYALU

NAVEEN MIRIYALU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10831659
    Abstract: A method handles cache misses using a Scope Resolution Tag Buffer (SRTB). A cache controller assigns each data block in L2 cache with an n-bit value, where the n-bit value describes a quantity of occurrences in which the data block has been accessed, and where the cache controller increments the n-bit value in one or more data blocks in the first level memory cache each time the one or more data blocks are accessed. The cache controller evicts a particular data block from the L2 cache, and stores a particular data block address where the particular data block is now stored in a Scope Resolution Tag Buffer (SRTB). The information in the SRTB is used to locate which cache or memory contains the particular data block in the event of a subsequent cache miss in the L2 cache.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Srinivas B. Purushotham, Naveen Miriyalu, Venkata K. Tavva
  • Publication number: 20200104258
    Abstract: A method handles cache misses using a Scope Resolution Tag Buffer (SRTB). A cache controller assigns each data block in L2 cache with an n-bit value, where the n-bit value describes a quantity of occurrences in which the data block has been accessed, and where the cache controller increments the n-bit value in one or more data blocks in the first level memory cache each time the one or more data blocks are accessed. The cache controller evicts a particular data block from the L2 cache, and stores a particular data block address where the particular data block is now stored in a Scope Resolution Tag Buffer (SRTB). The information in the SRTB is used to locate which cache or memory contains the particular data block in the event of a subsequent cache miss in the L2 cache.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 2, 2020
    Inventors: SRINIVAS B. PURUSHOTHAM, NAVEEN MIRIYALU, VENKATA K. TAVVA