Abstract: A processor includes a processor core including an execution unit to execute instructions, and a cache memory. The cache memory includes a controller to update each of a plurality of stale indicators in response to a lazy flush instruction. Each stale indicator is associated with respective data, and each updated stale indicator is to indicate that the respective data is stale. The cache memory also includes a plurality of cache lines. Each cache line is to store corresponding data and a foreground tag that includes a respective virtual address associated with the corresponding data, and that includes the associated stale indicator. Other embodiments are described as claimed.

Abstract: In one embodiment, the present invention includes an apparatus having an estimation logic to estimate a dynamic capacitance of a processor circuit of a processor during a plurality of processor cycles, a power gate calculator to calculate a control value for a power gate circuit coupled to a load line and between a voltage regulator and the processor circuit based on the dynamic capacitance estimate, and a controller to control an impedance of the power gate circuit based on the control value. Other embodiments are described and claimed.

Abstract: Hardware checkpoints may be used to mark software-based speculation regions. An instruction may be provided at the beginning of a speculation region and at the end of the speculation region. If an exception occurs during the speculation region, a hardware rollback may be occurred. The hardware rollback rolls back to the instruction at the beginning of the speculation region. The hardware may take a checkpoint by taking a register snapshot and treating future memory updates as tentative. When the instruction marking the end of the speculation is reached, all the tentative memory updates are committed and the previously taken register snapshot is discarded.

Abstract: A technique includes communicating a message to a dynamic translator in response to a change, which affects the validity of a translation that is performed by the dynamic translator.