Patents by Inventor Naveen Prabhu
Naveen Prabhu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240211896Abstract: Techniques for runtime optimizations to data models for facility maintenance operations are described. In operation, a custom request from a user to modify a data model of a facility, where the data model is indicative of information corresponding to assets monitored in the facility, and where the data model of the facility includes asset data corresponding to each asset of the facility and key performance indicators (KPIs) corresponding to each asset of the facility. A category of the custom request is then identified to generate a query list corresponding to the category of custom request for modifying asset data in the data model, where the custom request includes at least one of updating asset data corresponding to an asset of the facility and introducing new asset data in the data model. A custom input from the user is then received in response to the query list generated and modifying the data model in correspondence to the custom input.Type: ApplicationFiled: December 22, 2023Publication date: June 27, 2024Inventors: Jayalaxmi Telang, Ronny Scherf, Manu Taranath, Naveen Prabhu, Nishit Nagar
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Publication number: 20240088455Abstract: Disclosed herein are novel or improved separators, battery separators, lead battery separators, batteries, cells, and/or methods of manufacture and/or use of such separators, battery separators, lead battery separators, cells, and/or batteries. In accordance with at least certain embodiments, the present disclosure or invention is directed to novel or improved battery separators for lead acid batteries. In addition, disclosed herein are methods, systems and battery separators for enhancing battery life, reducing active material shedding, reducing grid and spine corrosion, reducing failure rate reducing acid stratification and/or improving uniformity in at least lead acid batteries, in particular batteries for electric rickshaws. In accordance with at least particular embodiments, the present disclosure or invention is directed to an improved separator for lead acid batteries wherein the separator includes improved membrane profiles, improved coatings, improved configurations, and/or the like.Type: ApplicationFiled: November 20, 2023Publication date: March 14, 2024Inventors: Surendra Kumar Mittal, Naveen Prabhu Shanmugam
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Patent number: 11862769Abstract: Disclosed herein are novel or improved separators, battery separators, lead battery separators, batteries, cells, and/or methods of manufacture and/or use of such separators, battery separators, lead battery separators, cells, and/or batteries. In accordance with at least certain embodiments, the present disclosure or invention is directed to novel or improved battery separators for lead acid batteries. In addition, disclosed herein are methods, systems and battery separators for enhancing battery life, reducing active material shedding, reducing grid and spine corrosion, reducing failure rate reducing acid stratification and/or improving uniformity in at least lead acid batteries, in particular batteries for electric rickshaws. In accordance with at least particular embodiments, the present disclosure or invention is directed to an improved separator for lead acid batteries wherein the separator includes improved membrane profiles, improved coatings, improved configurations, and/or the like.Type: GrantFiled: January 11, 2017Date of Patent: January 2, 2024Assignee: Daramic, LLCInventors: Surendra Kumar Mittal, Naveen Prabhu Shanmugam
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Publication number: 20230376215Abstract: An example of a memory device may comprise NAND media with a plurality of decks, and circuitry coupled to the NAND media to control access to a superblock of memory cells aligned along a pillar of the NAND media, wherein the superblock includes at least a first block that corresponds to memory cells aligned along the pillar in a first deck of the plurality of decks and a second block that corresponds to memory cells aligned along the pillar in a second deck of the plurality of decks, configure the NAND media in a first program mode for the first block of the superblock, and configure the NAND media in a second program mode for the second block of the superblock. Other examples are disclosed and claimed.Type: ApplicationFiled: December 21, 2022Publication date: November 23, 2023Applicant: Intel NDTM US LLCInventors: Aliasgar S Madraswala, Xin Sun, Naveen Prabhu Vittal Prabhu, Sagar Upadhyay
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Publication number: 20230229350Abstract: A storage device includes a storage array with multiple planes organized as plane groups, where the planes of a plane group receive and process commands in parallel. The storage device includes a storage controller that receives a command from a host controller. In response to receipt of the command the storage controller provides ready information for all planes to the host controller. The multiple planes can optionally have independent multiplane read operation (IMPRO). Each plane group can have a first plane and a second plane, and the storage controller can optionally read data from the first plane of a plane group in response to a virtual ready signal for the first plane, before the second plane of the plane group is ready.Type: ApplicationFiled: March 23, 2023Publication date: July 20, 2023Inventors: Aliasgar S. MADRASWALA, Naveen Prabhu VITTAL PRABHU, Vinaya HARISH, Sanket Sanjay WADYALKAR
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Publication number: 20230229356Abstract: A storage device includes a storage array with multiple planes organized as plane groups, where the planes of a plane group receive and process commands in parallel. The storage device includes a storage controller that receives a command from a host controller. In response to receipt of the command the storage controller provides ready information for all planes to the host controller. The multiple planes can optionally have independent multiplane read operation (IMPRO). Each plane group can have a first plane and a second plane, and the storage controller can optionally read data from the first plane of a plane group in response to a virtual ready signal for the first plane, before the second plane of the plane group is ready.Type: ApplicationFiled: March 23, 2023Publication date: July 20, 2023Inventors: Aliasgar S. MADRASWALA, Naveen Prabhu VITTAL PRABHU, Vinaya HARISH, Sanket Sanjay WADYALKAR
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Patent number: 11705582Abstract: An exemplary hybrid battery separator is provided with a porous sheet with a folded bottom edge and joined lateral edges that form a pocket. The folded bottom edge may have one or more openings or slits. The hybrid separators of the present disclosure are particularly useful for flat-plate cycling batteries. The separators of the present disclosure may effectively enhance the battery re-chargeability and the backup time. In addition, the separators of the present disclosure may contribute to the reduction of water loss in the battery, lowering the maintenance needs in service. It is expected that batteries having the separators of the present disclosure may be useful in various applications, such as in inverters, golf carts, as well as solar and traction applications.Type: GrantFiled: May 29, 2020Date of Patent: July 18, 2023Assignee: Daramic, LLCInventors: Surendra Kumar Mittal, Naveen Prabhu Shanmugam, J. Kevin Whear, Eric H. Miller
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Publication number: 20230185453Abstract: The size of page map memory in a NAND flash device used to store page related information is decreased by embedding page type in a row address. The row address is received by the NAND flash device from the host on the data bus in a six-cycle sequence. The received row address is used to decode a physical page address received during the row address cycle to obtain a word line and a block segment number for a block segment in the word line in the NAND flash array. A same block segment number is used for each page type in the block segment.Type: ApplicationFiled: February 9, 2023Publication date: June 15, 2023Inventors: Aliasgar S. MADRASWALA, Shanmathi MOOKIAH, Pratyush CHANDRAPATI, Naveen Prabhu VITTAL PRABHU
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Publication number: 20220415380Abstract: Systems, apparatuses and methods may provide for technology that sends a first command to a NAND die, sends first address information to the NAND die, and sends a second command to the NAND die, wherein the first command and the second command define a first command sequence and wherein the first address information signal a beginning of a first asynchronous read request from a first plurality of planes. In one example, the technology also sends a second command sequence and second address information to the NAND die wherein the second command sequence signals an end of the first asynchronous read request.Type: ApplicationFiled: June 24, 2021Publication date: December 29, 2022Inventors: Naveen Prabhu Vittal Prabhu, Aliasgar S. Madraswala, Bharat Pathak, Binh Ngo, Netra Mahuli, Ahsanur Rahman
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Publication number: 20220158305Abstract: New, improved or optimized battery separators, Z wrap separators, Z wrap serrated rib separators, Z wrap serrated rib separators for tubular batteries, components, cells, modules, systems, batteries, tubular batteries, industrial batteries, inverter batteries, batteries for heavy or light industrial applications, forklift batteries, float charged batteries, inverters, accumulators, methods, profiles, additives, compositions, composites, mixes, coatings, and/or related methods of Z wrapping separators, Z wrapping separators on electrodes of tubular batteries, water retention, water loss prevention, improved charge acceptance, production, use, and/or related Z wrapping equipment, and/or combinations thereof.Type: ApplicationFiled: January 16, 2020Publication date: May 19, 2022Inventors: Baiju Parasuraman, Ahila Krishnamoorthy, Naveen Prabhu Shanmugam, Sankara Valli T. Nayagam, Marimuthu Elangovan, Santanu Chatterjee
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Patent number: 11061762Abstract: A memory device that has been programmed to store a single bit or multiple bits can perform a determination of a number of threshold voltages in one or more threshold voltage level regions. Based on the number of threshold voltages meeting or exceeding a threshold level, a page of bits can be read and if the bit error rate of the page of bits is below a threshold rate, the page of bits can be stored in the cells together with other bits stored in the cells and a provided additional page of bits. However, if the bit error rate of the page of bits is at or above the threshold rate, then the bit or bits stored in the cells can be error corrected and stored together with a provided additional page of bits.Type: GrantFiled: February 4, 2019Date of Patent: July 13, 2021Assignee: Intel CorporationInventors: Naveen Prabhu Vittal Prabhu, Bharat M. Pathak, Aliasgar S. Madraswala, Yogesh B. Wakchaure, Violante Moschiano, Walter Di Francesco, Michele Incarnati, Antonino Giuseppe La Spina
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Publication number: 20200295335Abstract: An exemplary hybrid battery separator is provided with a porous sheet with a folded bottom edge and joined lateral edges that form a pocket. The folded bottom edge may have one or more openings or slits. The hybrid separators of the present disclosure are particularly useful for flat-plate cycling batteries. The separators of the present disclosure may effectively enhance the battery re-chargeability and the backup time. In addition, the separators of the present disclosure may contribute to the reduction of water loss in the battery, lowering the maintenance needs in service. It is expected that batteries having the separators of the present disclosure may be useful in various applications, such as in inverters, golf carts, as well as solar and traction applications.Type: ApplicationFiled: May 29, 2020Publication date: September 17, 2020Inventors: Surendra Kumar Mittal, Naveen Prabhu Shanmugam, J. Kevin Whear, Eric H. Miller
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Publication number: 20200250028Abstract: A memory device that has been programmed to store a single bit or multiple bits can perform a determination of a number of threshold voltages in one or more threshold voltage level regions. Based on the number of threshold voltages meeting or exceeding a threshold level, a page of bits can be read and if the bit error rate of the page of bits is below a threshold rate, the page of bits can be stored in the cells together with other bits stored in the cells and a provided additional page of bits. However, if the bit error rate of the page of bits is at or above the threshold rate, then the bit or bits stored in the cells can be error corrected and stored together with a provided additional page of bits.Type: ApplicationFiled: February 4, 2019Publication date: August 6, 2020Inventors: Naveen Prabhu VITTAL PRABHU, Bharat M. PATHAK, Aliasgar S. MADRASWALA, Yogesh B. WAKCHAURE, Violante MOSCHIANO, Walter DI FRANCESCO, Michele INCARNATI, Antonino Giuseppe LA SPINA
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Patent number: 10693118Abstract: An exemplary hybrid battery separator is provided with a porous sheet with a folded bottom edge and joined lateral edges that form a pocket. The folded bottom edge may have one or more openings or slits. The hybrid separators of the present disclosure are particularly useful for flat-plate cycling batteries. The separators of the present disclosure may effectively enhance the battery re-chargeability and the backup time. In addition, the separators of the present disclosure may contribute to the reduction of water loss in the battery, lowering the maintenance needs in service. It is expected that batteries having the separators of the present disclosure may be useful in various applications, such as in inverters, golf carts, as well as solar and traction applications.Type: GrantFiled: August 12, 2016Date of Patent: June 23, 2020Assignee: Daramic, LLCInventors: Surendra Kumar Mittal, Naveen Prabhu Shanmugam, J. Kevin Whear, Eric H. Miller
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Publication number: 20200160473Abstract: Methods, devices, and systems for generating an incident dossier are described herein. One device includes a memory, and a processor configured to execute executable instructions stored in the memory to import data associated with an incident associated with a site, wherein the data is in a number of different forms, receive a number of user inputs associated with the incident, and generate an incident dossier based on the data associated with the incident and the number of user inputs, wherein the incident dossier includes a timeline of the incident, a report of the incident, and a damage assessment of the incident.Type: ApplicationFiled: January 21, 2020Publication date: May 21, 2020Inventors: Anantha Padmanabha Rahul U, Jagmeet Puri, Magesh Lingan, Alok Mishra, Naveen Prabhu, Ronita De
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Patent number: 10572962Abstract: Methods, devices, and systems for generating an incident dossier are described herein. One device includes a memory, and a processor configured to execute executable instructions stored in the memory to import data associated with an incident associated with a site, wherein the data is in a number of different forms, receive a number of user inputs associated with the incident, and generate an incident dossier based on the data associated with the incident and the number of user inputs, wherein the incident dossier includes a timeline of the incident, a report of the incident, and a damage assessment of the incident.Type: GrantFiled: September 8, 2015Date of Patent: February 25, 2020Assignee: Honeywell International Inc.Inventors: Anantha Padmanabha Rahul U, Jagmeet Puri, Magesh Lingan, Alok Mishra, Naveen Prabhu, Ronita De
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Publication number: 20180349814Abstract: An adaptive analytics framework is provided. The adaptive analytics framework includes one or more customizable analytic blocks with a source code therein. Each analytic block is configured to receive input data associated with at least one business problem and to implement an analytic workflow to determine one or more solutions to the business problem. The framework also includes an integration module configured to facilitate integration of the one or more customizable analytic blocks with an external platform.Type: ApplicationFiled: April 24, 2018Publication date: December 6, 2018Applicant: Mu Sigma Business Solutions Pvt. Ltd.Inventors: Deepinder DHINGRA, Rajat SRIVASTAV, Vishwajit Yogenkumar VYAS, Naveen PRABHU
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Publication number: 20170200984Abstract: Disclosed herein are novel or improved separators, battery separators, lead battery separators, batteries, cells, and/or methods of manufacture and/or use of such separators, battery separators, lead battery separators, cells, and/or batteries. In accordance with at least certain embodiments, the present disclosure or invention is directed to novel or improved battery separators for lead acid batteries. In addition, disclosed herein are methods, systems and battery separators for enhancing battery life, reducing active material shedding, reducing grid and spine corrosion, reducing failure rate reducing acid stratification and/or improving uniformity in at least lead acid batteries, in particular batteries for electric rickshaws. In accordance with at least particular embodiments, the present disclosure or invention is directed to an improved separator for lead acid batteries wherein the separator includes improved membrane profiles, improved coatings, improved configurations, and/or the like.Type: ApplicationFiled: January 11, 2017Publication date: July 13, 2017Inventors: Surendra Kumar Mittal, Naveen Prabhu Shanmugam
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Publication number: 20170076239Abstract: Devices, methods, and systems for incident management analysis are described herein. One device includes a memory and a processor configured to execute executable instructions stored in the memory to receive information associated with management of a number of incidents at a site, wherein each respective incident is managed by an operator using a standard operating procedure associated with that incident, analyze the number of incidents using the received information, and provide the analysis of the number of incidents to a user.Type: ApplicationFiled: September 16, 2015Publication date: March 16, 2017Inventors: Anantha Padmanabha Rahul U, Jagmeet Puri, Magesh Lingan, Naveen Prabhu, Ambuj Nema, Balamurugan B, Ramesh A
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Publication number: 20170068422Abstract: Methods, devices, and systems for generating an incident dossier are described herein. One device includes a memory, and a processor configured to execute executable instructions stored in the memory to import data associated with an incident associated with a site, wherein the data is in a number of different forms, receive a number of user inputs associated with the incident, and generate an incident dossier based on the data associated with the incident and the number of user inputs, wherein the incident dossier includes a timeline of the incident, a report of the incident, and a damage assessment of the incident.Type: ApplicationFiled: September 8, 2015Publication date: March 9, 2017Inventors: Anantha Padmanabha Rahul U, Jagmeet Puri, Magesh Lingan, Alok Mishra, Naveen Prabhu, Ronita De