Abstract: In one embodiment, a BIST (built-in self-test) engine performs BIST testing of embedded memory in an integrated circuit device (e.g., an FPGA) via an (e.g., hard-wired, dedicated, low-latency) bus from the configuration bitstream engine. During BIST testing, data is written into the embedded memory at-speed, which may require the bitstream engine to produce a higher frequency than originally used for configuration. Between consecutive write operations, the BIST engine is capable of reading the previously written set of data from the embedded memory and comparing that read-back data with the corresponding original set of data to determine whether a BIST error has occurred. By performing back-to-back write/read-back operations faster than the configuration speed and using a dedicated W/RB bus, BIST testing can be optimally performed without false-positive-invoking delays and undesirable resource utilization.

Abstract: In one embodiment, a BIST (built-in self-test) engine performs BIST testing of embedded memory in an integrated circuit device (e.g., an FPGA) via an (e.g., hard-wired, dedicated, low-latency) bus from the configuration bitstream engine. During BIST testing, data is written into the embedded memory at-speed, which may require the bitstream engine to produce a higher frequency than originally used for configuration. Between consecutive write operations, the BIST engine is capable of reading the previously written set of data from the embedded memory and comparing that read-back data with the corresponding original set of data to determine whether a BIST error has occurred. By performing back-to-back write/read-back operations faster than the configuration speed and using a dedicated W/RB bus, BIST testing can be optimally performed without false-positive-invoking delays and undesirable resource utilization.

Abstract: In certain embodiment, built-in self-test (BIST) circuitry for multiport memory comprises a configurable address generator and a configurable data generator. The configurable address generator can be configured to concurrently generate first and second logical memory addresses corresponding to physically neighboring first and second memory cells of the multiport memory for any selected memory mode of a plurality of available memory modes having different column-multiplexing schemes. The configurable data generator can be configured to concurrently generate two sets of data for the selected memory mode, such that (i) the first set of data is written into and read from the multiport memory via a first memory port using the first logical memory address and (ii) the second set of data is written into and read from the multiport memory via a second memory port using the second logical memory address. The BIST circuitry enables efficient, physically aware built-in self-testing.