Abstract: Various embodiments comprise systems, methods, architectures, mechanisms or apparatus for providing programmable or pre-programmed in-memory computing operations.

Abstract: Systems and methods disclosed herein provide for a passive backscattering beamformer based on large-area electronics (LAE). Low power is critical for distributed nodes in future IoT/5G networks. A key emerging solution is using ubiquitous 2.4 GHz Wi-Fi infrastructure with passive backscattering nodes, for low-power communication. LAE enables monolithic integration of devices over large and flexible substrates, with recent advances into the gigahertz regime opening new opportunities for wireless systems. An LAE passive backscattering beamformer is chosen that is capable of (1) enhancing the backscattered signal power in a scalable manner enabled by LAE's monolithic integrability over meter-scale area; (2) configuration between constructive/destructive beamforming; (3) frequency-shift keying for data modulation and SNR enhancement, by shifting the signal away from the incident interferer; and (4) frequency division multiplexing for increasing data bandwidth.

Abstract: Systems and methods are provided for reducing power in in-memory computing, matrix-vector computations, and neural networks. An apparatus for in-memory computing using charge-domain circuit operation includes transistors configured as memory bit cells, transistors configured to perform in-memory computing using the memory bit cells, capacitors configured to store a result of in-memory computing from the memory bit cells, and switches, wherein, based on a setting of each of the switches, the charges on at least a portion of the plurality of capacitors are shorted together. Shorting together the plurality of capacitors yields a computation result.

Abstract: Various embodiments comprise systems, methods, architectures, mechanisms or apparatus for providing programmable or pre-programmed in-memory computing operations.

Abstract: Various embodiments comprise systems, methods, architectures, mechanisms, apparatus, and improvements thereof for scaling and summing a plurality of weighted-data-representative analog signals provided by columns of in-memory computing bit cells within an N×M array of bit cells such that analog accumulation or summation of the weighted-data-representative analog signals provides a scaled result for further processing.

Abstract: Various embodiments comprise systems, methods, architectures, mechanisms or apparatus for providing programmable or pre-programmed in-memory computing operations.

Abstract: Various embodiments comprise systems, methods, architectures, mechanisms, apparatus, and improvements thereof for in-memory computing using charge-domain circuit operation to provide energy efficient, high speed, capacitor-based in-memory computing. Various embodiments contemplate controlling input signal presentation within in-memory computing structures/macros in accordance with predefined or dynamic switch selection criteria to reduce energy consumption associated with charging and/or discharging summing capacitors during reset and evaluation operating modes of multiplying bit-cells (M-BCs).

Abstract: Various embodiments comprise systems, methods, architectures, mechanisms or apparatus for providing programmable or pre-programmed in-memory computing operations.

Abstract: Systems and methods are provided for reducing power in in-memory computing, matrix-vector computations, and neural networks. An apparatus for in-memory computing using charge-domain circuit operation includes transistors configured as memory bit cells, transistors configured to perform in-memory computing using the memory bit cells, capacitors configured to store a result of in-memory computing from the memory bit cells, and switches, wherein, based on a setting of each of the switches, the charges on at least a portion of the plurality of capacitors are shorted together. Shorting together the plurality of capacitors yields a computation result.

Abstract: Various embodiments comprise systems, methods, architectures, mechanisms and apparatus for providing programmable or pre-programmed in-memory computing (IMC) operations via an array of configurable IMC cores interconnected by a configurable on-chip network to support scalable execution and dataflow of an application mapped thereto.

Abstract: A heterogeneous microprocessor configured to perform classification on an input signal. The heterogeneous microprocessor includes a die with a central processing unit (CPU) a programmable feature-extraction accelerator (FEA) and a classifier. The FEA is configured to perform feature extraction on the input signal to generate feature data. The classifier is configured to perform classification on the feature data and the CPU is configured to provide processing after classification. The FEA may be configured with a plurality of Gene-Computation (GC) Cores. The FEA may be configured for genetic programing with gene depth constraints, gene number constraints and base function constraints. The classifier may be a support-vector machine accelerator (SVMA). The SVMA may include training data based on error-affected feature data. The heterogeneous microprocessor may also include an automatic-programming & classifier training module.

Abstract: Systems and methods are provided for reducing power in in-memory computing, matrix-vector computations, and neural networks. An apparatus for in-memory computing using charge-domain circuit operation includes transistors configured as memory bit cells, transistors configured to perform in-memory computing using the memory bit cells, capacitors configured to store a result of in-memory computing from the memory bit cells, and switches, wherein, based on a setting of each of the switches, the charges on at least a portion of the plurality of capacitors are shorted together. Shorting together the plurality of capacitors yields a computation result.

Abstract: Various embodiments comprise systems, methods, architectures, mechanisms, apparatus, and improvements thereof for in-memory computing using charge-domain circuit operation to provide energy efficient, high speed, capacitor-based in-memory computing. Various embodiments contemplate controlling input signal presentation within in-memory computing structures/macros in accordance with predefined or dynamic switch selection criteria to reduce energy consumption associated with charging and/or discharging summing capacitors during reset and evaluation operating modes of multiplying bit-cells (M-BCs).

Abstract: Various embodiments comprise systems, methods, architectures, mechanisms or apparatus for providing programmable or pre-programmed in-memory computing operations.

Abstract: A weak binary classifier configured to receive an input signal for classification and generate a classification output is disclosed. The weak binary classifier includes a plurality of weighting amplifier stages, each weighting amplifier stage being configured to receive the input signal for classification and a weighting input derived from a classifier model and generate a weighted input signal, the plurality of weighting amplifier stages being configured to generate a plurality of positive weighted input signals coupled to a positive summing node and a plurality of negative weighted input signals coupled to a negative summing node. The weak binary classifier also includes a comparator having a non-inverting input coupled to the positive summing node and an inverting input coupled to the negative summing node and being configured to generate a weak classification output based on the plurality of weighted input signals.

Abstract: Systems and methods are provided for reducing power in in-memory computing, matrix-vector computations, and neural networks. An apparatus for in-memory computing using charge-domain circuit operation includes transistors configured as memory bit cells, transistors configured to perform in-memory computing using the memory bit cells, capacitors configured to store a result of in-memory computing from the memory bit cells, and switches, wherein, based on a setting of each of the switches, the charges on at least a portion of the plurality of capacitors are shorted together. Shorting together the plurality of capacitors yields a computation result.

Abstract: Embodiments of the present invention are directed to a computer implemented web based application testing system and method for testing at least one software application. The system and method receiving at least one test selection from a user using a user interface at a display device. The test selection may include at least one of a feature, a scenario, a background and a predefined condition. A feature file generation engine may then generate at least one feature file based on the test selection. Also, the feature file may be stored in a non-transitory computer memory. A feature file execution engine may execute the feature file and generate at least one execution result. A reporting engine may then generate a report based on the execution result. The execution result may then be displayed at the web dashboard.

Abstract: A heterogeneous microprocessor configured to perform classification on an input signal. The heterogeneous microprocessor includes a die with a central processing unit (CPU) a programmable feature-extraction accelerator (FEA) and a classifier. The FEA is configured to perform feature extraction on the input signal to generate feature data. The classifier is configured to perform classification on the feature data and the CPU is configured to provide processing after classification. The FEA may be configured with a plurality of Gene-Computation (GC) Cores. The FEA may be configured for genetic programing with gene depth constraints, gene number constraints and base function constraints. The classifier may be a support-vector machine accelerator (SVMA). The SVMA may include training data based on error-affected feature data. The heterogeneous microprocessor may also include an automatic-programming & classifier training module.

Abstract: A three dimensional touch sensing system having a touch surface configured to detect a touch input located above the touch surface is disclosed. The system includes a plurality of capacitive touch sensing electrodes disposed on the touch surface, each electrode having a baseline capacitance and a touch capacitance based on the touch input. An oscillating plane is disposed below the touch surface. A touch detector is configured to drive one of the touch sensing electrodes with an AC signal having a frequency that shifts from a baseline frequency to a touch frequency based on the change in electrode capacitance from the baseline capacitance to the touch capacitance. The touch detector is configured to drive the oscillating plane to the touch frequency.

Abstract: A three dimensional touch sensing system having a touch surface configured to detect a touch input located above the touch surface is disclosed. The system includes a plurality of capacitive touch sensing electrodes disposed on the touch surface, each electrode having a baseline capacitance and a touch capacitance based on the touch input. An oscillating plane is disposed below the touch surface. A touch detector is configured to drive one of the touch sensing electrodes with an AC signal having a frequency that shifts from a baseline frequency to a touch frequency based on the change in electrode capacitance from the baseline capacitance to the touch capacitance. The touch detector is configured to drive the oscillating plane to the touch frequency.