Patents by Inventor Naveendran Balasingam

Naveendran Balasingam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210231746
    Abstract: Described is an apparatus which comprises: a first voltage regulator (VR) having a reference input node; and a first multiplexer to provide a reference voltage to the reference input node and operable to select one of at least two different reference voltages as the reference voltage.
    Type: Application
    Filed: April 15, 2021
    Publication date: July 29, 2021
    Applicant: Intel Corporation
    Inventors: Sankaran M. Menon, Vasudev Bibikar, P. Reddy Sahajananda, Sunghyun Koh, Naveendran Balasingam
  • Patent number: 10996283
    Abstract: Described is an apparatus which comprises: a first voltage regulator (VR) having a reference input node; and a first multiplexer to provide a reference voltage to the reference input node and operable to select one of at least two different reference voltages as the reference voltage.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: May 4, 2021
    Assignee: Intel Corporation
    Inventors: Sankaran M. Menon, Vasudev Bibikar, P. Reddy Sahajananda, Sunghyun Koh, Naveendran Balasingam
  • Publication number: 20180128878
    Abstract: Described is an apparatus which comprises: a first voltage regulator (VR) having a reference input node; and a first multiplexer to provide a reference voltage to the reference input node and operable to select one of at least two different reference voltages as the reference voltage.
    Type: Application
    Filed: October 9, 2017
    Publication date: May 10, 2018
    Inventors: SANKARAN M. MENON, VASUDEV BIBIKAR, SAHAJANANDA REDDY P, SUNGHYUN KOH, NAVEENDRAN BALASINGAM
  • Patent number: 9784791
    Abstract: Described is an apparatus which comprises: a first voltage regulator (VR) having a reference input node; and a first multiplexer to provide a reference voltage to the reference input node and operable to select one of at least two different reference voltages as the reference voltage.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: October 10, 2017
    Assignee: Intel Corporation
    Inventors: Sankaran M. Menon, Vasudev Bibikar, P. Reddy Sahajananda, Sunghyun Koh, Naveendran Balasingam
  • Publication number: 20160018462
    Abstract: Described is an apparatus which comprises: a first voltage regulator (VR) having a reference input node; and a first multiplexer to provide a reference voltage to the reference input node and operable to select one of at least two different reference voltages as the reference voltage.
    Type: Application
    Filed: July 18, 2014
    Publication date: January 21, 2016
    Inventors: SANKARAN MENON, VASUDEV BIBIKAR, SAHAJANANDA REDDY P, SUNGHYUN KOH, NAVEENDRAN BALASINGAM
  • Patent number: 7403027
    Abstract: An apparatus and method for selecting and outputting test patterns and internal signals during various SHBI modes of operation. The apparatus may include multiple input/output (I/O) pins, one or more functional blocks, a Self-Heat Burn-In (SHBI) state machine that is coupled to the I/O pins and the one or more functional blocks, and a logic selector circuitry that is coupled to the SHBI state machine and the one or more functional blocks. The SHBI state machine may provide to the I/O pins with first one or more test patterns during a first SHBI mode of operation, and to provide the one or more functional blocks with second one or more test patterns during a second SHBI mode of operation. The logic selector circuitry is configured to select and output the first one or more test patterns to stress the I/O pins during the first SHBI mode of operation, and to select and output internal signals of the one more functional blocks during the second SHBI mode of operation.
    Type: Grant
    Filed: October 30, 2006
    Date of Patent: July 22, 2008
    Assignee: Intel Corporation
    Inventors: Yuen Tat Lee, Soon Eng Low, Naveendran Balasingam
  • Publication number: 20080100327
    Abstract: An apparatus and method for selecting and outputting test patterns and internal signals during various SHBI modes of operation. The apparatus may include multiple input/output (I/O) pins, one or more functional blocks, a Self-Heat Burn-In (SHBI) state machine that is coupled to the I/O pins and the one or more functional blocks, and a logic selector circuitry that is coupled to the SHBI state machine and the one or more functional blocks. The SHBI state machine may provide to the I/O pins with first one or more test patterns during a first SHBI mode of operation, and to provide the one or more functional blocks with second one or more test patterns during a second SHBI mode of operation. The logic selector circuitry is configured to select and output the first one or more test patterns to stress the I/O pins during the first SHBI mode of operation, and to select and output internal signals of the one more functional blocks during the second SHBI mode of operation.
    Type: Application
    Filed: October 30, 2006
    Publication date: May 1, 2008
    Inventors: Yuen Tat Lee, Soon Eng Low, Naveendran Balasingam