Abstract: Methods for determining induced noise on a given victim by a set of aggressor signals are presented, and for identifying the worst case aggressor switching time alignment that causes the worst case victim noise. The method removes circuit analysis pessimism related to simultaneous switching noise (SSN) in a circuit design tool by determining physically impossible combinations of victim-aggressor input/output (I/O) pins in a circuit design and culling out the impossible combinations from the list of possible victim-aggressor combinations. The method further performs a switching window SSN analysis of the circuit design with a common uncertainty removal algorithm taking into consideration the list of possible victim-aggressor combinations, and determines the maximum voltage noise induced on I/O pins of the circuit design. The results of the noise analysis are displayed to the user.

Abstract: Methods and apparatus for reducing simultaneous switching noise (SSN) in an integrated circuit (IC) designed with a computer aided design (CAD) tool are presented. In one method, value assignments for parameters of the IC are received by the CAD tool. The value assignments are entered as a range of value. The minimum and the maximum path delays for each Input/Output (I/O) pin in an I/O block are determined such that the received value assignments are satisfied. The actual switching times of the I/O pins are spread out in time to decrease SSN in the I/O pins. The switching times are spread out so that the switching times fall between the minimum and the maximum path delay for the corresponding I/O pin.

Abstract: Methods, computer programs, and Integrated Circuits (IC) for minimizing Simultaneous Switching Noise (SSN) in the design of an IC are presented. In one embodiment, the method includes moving a candidate pin of the IC in an initial input/output (I/O) layout to create a candidate I/O layout. Further, in one operation the method calculates a first performance cost for the initial I/O layout and a second performance cost for the candidate I/O layout. The first and the second performance costs are based on an SSN cost for the initial layout and on an SSN cost for the candidate layout respectively. The method selects the layout to design the IC that has the lowest performance cost. The method operations are performed during the placement phase of an IC Computer Aided Design (CAD) tool.

Abstract: Methods and apparatus for reducing simultaneous switching noise (SSN) in an integrated circuit (IC) designed with a computer aided design (CAD) tool are presented. In one method, value assignments for parameters of the IC are received by the CAD tool. The value assignments are entered as a range of value assignments or as a list of possible value assignments. Further, the method includes an operation for determining the minimum and the maximum path delays for each Input/Output (I/O) pin in an I/O block such that the received value assignments are satisfied. The actual switching times of the I/O pins are spread out in time to decrease SSN in the I/O pins. The switching times are spread out so that the switching times fall between the minimum and the maximum path delay for the corresponding I/O pin. Additionally, other method operations are included for routing paths to the I/O pins to meet the actual switching times and for creating a design for the IC that meets the actual switching times.

Abstract: Methods, computer programs, and systems for designing an electronic component are presented. One method calculates a first Simultaneous Switching Noise (SSN) on Input/Output (IO) pins using a first configuration of the electronic component. A setting or a placement of a chosen IO pin is changed to obtain a second configuration of the electronic component, and a second SSN on IO pins is obtained based on the results of the first SSN and based on new SSN calculations related to the changed setting or placement. The second SSN on an IO pin, other than the chosen IO pin, is calculated by subtracting from the first SSN on the IO pin the SSN caused by the chosen IO pin calculated in the first SSN, and by adding an incremental SSN caused by the chosen IO pin on the pin in the second configuration. The method further includes the operation of creating a design for the electronic component with either the first or the second configuration based on the results of the first and the second SSN.

Abstract: A method for providing transistor threshold voltage compensation in an FPGA integrated circuit with a plurality of programmable circuit blocks includes measuring the effective transistor threshold voltage values of each programmable circuit block and adjusting the effective transistor threshold voltage values of each programmable circuit block to compensate for the difference between the measured effective transistor threshold voltage value and the target effective transistor threshold voltage value.

Abstract: Asymmetric SRAM cell designs exploiting data storage patterns found in ordinary software programs wherein most of the bits stored are zeroes for data and instruction streams. The asymmetric SRAM cell designs offer lower leakage power with little impact on latency. In asymmetric SRAM cells, selected transistors are “weakened” to reduce leakage current when the cell is storing a zero. Transistor weakening may be achieved by using higher voltage threshold transistors, by varying transistor geometries, or other means. In addition, a novel sense amplifier design is provided that leverages the asymmetric nature of the asymmetric SRAM cells to offer cell read times that are comparable with conventional symmetric SRAM cells. Lastly, cache memory designs are provided that are based on asymmetric SRAM cells offering leakage power reduction while maintaining high performance, comparable noise margins, and stability with respect to conventional cache memories.

Abstract: Asymmetric SRAM cell designs exploiting data storage patterns found in ordinary software programs wherein most of the bits stored are zeroes for data and instruction streams. The asymmetric SRAM cell designs offer lower leakage power with little impact on latency. In asymmetric SRAM cells, selected transistors are “weakened” to reduce leakage current when the cell is storing a zero. Transistor weakening may be achieved by using higher voltage threshold transistors, by varying transistor geometries, or other means. In addition, a novel sense amplifier design is provided that leverages the asymmetric nature of the asymmetric SRAM cells to offer cell read times that are comparable with conventional symmetric SRAM cells. Lastly, cache memory designs are provided that are based on asymmetric SRAM cells offering leakage power reduction while maintaining high performance, comparable noise margins, and stability with respect to conventional cache memories.