Abstract: A latch circuit that has a dynamic mode and a static mode is provided. Clock signals are generated specifically for a feedback path of a storage circuit in the latch circuit. The generated clock signals include transitions that cause clocked NMOS and PMOS devices in the feedback path to function, and for other input clock frequencies, the generated clock signals do not include transitions that cause the clocked PMOS and NMOS devices to be active, and have states that cause clocked PMOS and NMOS devices to be inactive.

Abstract: The present invention relates to providing a system clock signal that is based on either a first clock signal that is capable of being frequency-corrected or a second clock signal that is not capable of being frequency-corrected, depending on system needs. When the system clock signal is based on the second clock signal, all or part of the circuitry that provides the first clock signal may be disabled or powered-down to reduce power consumption. A multiplexer may be used to select either the first or the second clock signal to provide the system clock signal to system circuitry. The system circuitry may be intolerant of phase-jumps in the system clock signal; therefore, before the multiplexer transitions between the first and the second clock signals, the first clock signal may be phase-adjusted to bring it into phase-alignment with the second clock signal.

Abstract: An integrated level shifter circuit converts an input signal having a first voltage potential to an output signal having a second voltage potential. The level shifter circuit provides circuit operation between the sections when the voltage potential of the input logic signal is converted to the output logic signal having lower voltage potential. For logic signals transmitted between sections of an integrated circuit operating with different supply voltages. The level shift circuit for each input includes two transistors and a voltage divider circuit having two resistors in series. The values of the resistors are selected to yield a desired output voltage at a node between the two resistors. In effect, the resistors lessen the a full 0.9 volt diode drop to yield a level shift which is a fraction of a diode drop. A capacitor in parallel with the resistor provides a path for AC signals and increases both the speed and bandwidth of the level shifter.

Abstract: An integrated level shifter circuit converts an input signal having a first voltage potential to an output signal having a second voltage potential. The level shifter circuit provides circuit operation between the sections when the voltage potential of the input logic signal is converted to the output logic signal having lower voltage potential. For logic signals transmitted between sections of an integrated circuit operating with different supply voltages. The level shift circuit for each input includes two transistors and a voltage divider circuit having two resistors in series. The values of the resistors are selected to yield a desired output voltage at a node between the two resistors. In effect, the resistors lessen a full 0.9 volt diode drop to yield a level shift which is a fraction of a diode drop. A capacitor in parallel with the resistor provides a path for AC signals and increases both the speed and bandwidth of the level shifter.

Abstract: A current mode logic circuit having npn transistors coupled to an NMOS current source provides a substantially constant current when controlled by an opamp comparator. A gate of the NMOS current source is directly coupled to an output terminal of the opamp. A source of the NMOS transistor is connected to one of the inputs of the comparator opamp. Another input terminal is connected to voltage source. The opamp compares the two inputs and provides an output signal which ensures that the opamp will provide a substantially constant current source.

Abstract: A charge pump circuit for a phase locked loop includes series-connected FETs in which a reference current flows and other series-connected FETs in which sourcing and sinking currents flow. The junctions of the two series-connected FETs are connected to the non-inverting and inverting input terminals of an operational amplifier. The amplifier detects the voltage difference between a reference side junction and the output voltage of the charge pump circuit and provides an amplified voltage of the detected voltage difference. In response to the amplified voltage, the charge pump circuit sources to and sinks current from an external circuit to which the charge pump circuit is connected. Due to the definite and high input impedance of the operational amplifier, there is no mismatch between the source and the sink currents. A start-up FET initializes the charge pump circuit so that current flows in the series-connected FETs.

Abstract: A multi-ratio frequency divider, which is implemented in a BiCMOS (bipolar-complementary metal oxide semiconductor) circuit, includes a dual-modulus counter for dividing by P+1 and P. P+1 is a power of two and there is not necessary an additional flip-flop responsive to high input frequency, which consumes power due to bipolar transistor devices. An output from the counter is further divided by a variably set value. When its count reaches another set value, the division ratio of the dual-modulus counter is switched to another division ratio. When the further divided counter reaches the variably set value, a new cycle starts. The total division ratio of the multi-modulus frequency divider is a combination of the variably set division values, both being binary bit data. No decoder is necessary for converting an input division ratio to the set values.