Patents by Inventor Navienkumar Ramachandran Arumugam

Navienkumar Ramachandran Arumugam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multi-Voltage Complementary Metal Oxide Semiconductor Integrated Circuits Based On Always-On N-Well Architecture
    Publication number: 20180158823
    Abstract: Examples of multi-voltage (MV) complementary metal oxide semiconductor (CMOS) integrated circuits (ICs) based on always-on N-well architecture are described. An MV CMOS IC may include first CMOS cells, second CMOS cells, N-wells and always-on taps. Each first CMOS cell may have a supply terminal configured to receive a local supply voltage, and an N-well (NW) terminal configured to receive a global supply voltage. The second CMOS cells may include always-on CMOS cells. Each second CMOS cell may have a supply terminal configured to receive the global supply voltage, and an NW terminal configured to receive the global supply voltage. The NW terminal of at least one of the second CMOS cells and the NW terminal of at least one of the first CMOS cells may be formed in a first N-well of the one or more N-wells.
    Type: Application
    Filed: January 9, 2018
    Publication date: June 7, 2018
    Inventors: Senthilkumar Jayapal, Navienkumar Ramachandran Arumugam
  • Multi-voltage complementary metal oxide semiconductor integrated circuits based on always-on N-well architecture
    Patent number: 9905560
    Abstract: Examples of multi-voltage (MV) complementary metal oxide semiconductor (CMOS) integrated circuits (ICs) based on always-on N-well architecture are described. A MV CMOS IC may include first CMOS cells, second CMOS cells, N-wells and always-on taps. Each first CMOS cell may have a supply terminal configured to receive a local supply voltage, and an N-well (NW) terminal configured to receive a global supply voltage. The second CMOS cells may include always-on CMOS cells. Each second CMOS cell may have a supply terminal configured to receive the global supply voltage, and an NW terminal configured to receive the global supply voltage. The NW terminal of at least one of the second CMOS cells and the NW terminal of at least one of the first CMOS cells may be formed in a first N-well of the one or more N-wells.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: February 27, 2018
    Assignee: MEDIATEK SINGAPORE PTE. LTD.
    Inventors: Senthilkumar Jayapal, Navienkumar Ramachandran Arumugam
  • Multi-Voltage Complementary Metal Oxide Semiconductor Integrated Circuits Based On Always-On N-Well Architecture
    Publication number: 20160111424
    Abstract: Examples of multi-voltage (MV) complementary metal oxide semiconductor (CMOS) integrated circuits (ICs) based on always-on N-well architecture are described. A MV CMOS IC may include first CMOS cells, second CMOS cells, N-wells and always-on taps. Each first CMOS cell may have a supply terminal configured to receive a local supply voltage, and an N-well (NW) terminal configured to receive a global supply voltage. The second CMOS cells may include always-on CMOS cells. Each second CMOS cell may have a supply terminal configured to receive the global supply voltage, and an NW terminal configured to receive the global supply voltage. The NW terminal of at least one of the second CMOS cells and the NW terminal of at least one of the first CMOS cells may be formed in a first N-well of the one or more N-wells.
    Type: Application
    Filed: December 30, 2015
    Publication date: April 21, 2016
    Inventors: Senthilkumar Jayapal, Navienkumar Ramachandran Arumugam