Patents by Inventor Navin Acharya

Navin Acharya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Parallel processing in hardware accelerators communicably coupled with a processor
    Patent number: 10423414
    Abstract: In an embodiment, a device including a processor, a plurality of hardware accelerator engines and a hardware scheduler is disclosed. The processor is configured to schedule an execution of a plurality of instruction threads, where each instruction thread includes a plurality of instructions associated with an execution sequence. The plurality of hardware accelerator engines performs the scheduled execution of the plurality of instruction threads. The hardware scheduler is configured to control the scheduled execution such that each hardware accelerator engine is configured to execute a corresponding instruction and the plurality of instructions are executed by the plurality of hardware accelerator engines in a sequential manner. The plurality of instruction threads are executed by plurality of hardware accelerator engines in a parallel manner based on the execution sequence and an availability status of each of the plurality of hardware accelerator engines.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: September 24, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ajit Deepak Gupte, Mahesh Mehendale, Navin Acharya, Mel Alan Phipps
  • PARALLEL PROCESSING IN HARDWARE ACCELERATORS COMMUNICABLY COUPLED WITH A PROCESSOR
    Publication number: 20160132329
    Abstract: In an embodiment, a device including a processor, a plurality of hardware accelerator engines and a hardware scheduler is disclosed. The processor is configured to schedule an execution of a plurality of instruction threads, where each instruction thread includes a plurality of instructions associated with an execution sequence. The plurality of hardware accelerator engines performs the scheduled execution of the plurality of instruction threads. The hardware scheduler is configured to control the scheduled execution such that each hardware accelerator engine is configured to execute a corresponding instruction and the plurality of instructions are executed by the plurality of hardware accelerator engines in a sequential manner. The plurality of instruction threads are executed by plurality of hardware accelerator engines in a parallel manner based on the execution sequence and an availability status of each of the plurality of hardware accelerator engines.
    Type: Application
    Filed: November 12, 2014
    Publication date: May 12, 2016
    Inventors: Ajit Deepak Gupte, Mahesh Mehendale, Navin Acharya, Mel Alan Phipps