Patents by Inventor Navin Harwalkar
Navin Harwalkar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10469295Abstract: In one aspect, an apparatus includes: a mixer to receive a radio frequency (RF) signal and downconvert the RF signal into a second frequency signal; an amplifier coupled to the mixer to amplify the second frequency signal; an image rejection (IR) circuit coupled to the programmable gain amplifier (PGA) to orthogonally correct a gain and a phase of the amplified second frequency signal to output a corrected amplified second frequency signal; and a complex filter to filter the corrected amplified second frequency signal.Type: GrantFiled: October 31, 2017Date of Patent: November 5, 2019Assignee: SILICON LABORATORIES INC.Inventors: John M. Khoury, Navin Harwalkar
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Patent number: 10181868Abstract: An apparatus includes a radio-frequency (RF) receiver. The RF receiver includes a single-balanced passive mixer driven by the output of a low noise amplifier (LNA) and a passive filter driven by an output of the single-balanced passive mixer. The RF receiver further includes a programmable gain amplifier (PGA) having an input resistance that generates noise, where the PGA is driven by an output of the passive filter, and the noise generated by the input resistance of the PGA is suppressed.Type: GrantFiled: May 31, 2017Date of Patent: January 15, 2019Assignee: Silicon Laboratories Inc.Inventors: Navin Harwalkar, Arup Mukherji, John M. Khoury
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Patent number: 10164593Abstract: Embodiments of power detector circuits and related methods to compensate for undesired DC offsets generated within power detector circuits are disclosed. Input signals having input frequencies are received and converted to a magnitude signal, and reference signals are also generated. The magnitude signal may include a DC component proportional to a power of the input signal along with undesired DC offsets. The reference signal may include a DC component proportional to a power of at least one input reference signal along with undesired DC offsets. To compensate for errors introduced by the DC offsets, a programmable digital input signal is determined in a calibration mode and then applied to reference circuitry in a normal mode to compensate for the DC offsets. For the calibration mode, a difference between the magnitude signal and the reference signal is compared to a threshold value to generate a power detection output signal.Type: GrantFiled: September 7, 2017Date of Patent: December 25, 2018Assignee: Silicon Laboratories Inc.Inventors: Navin Harwalkar, John M. Khoury
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Publication number: 20180351593Abstract: An apparatus includes a radio-frequency (RF) receiver. The RF receiver includes a single-balanced passive mixer driven by the output of a low noise amplifier (LNA) and a passive filter driven by an output of the single-balanced passive mixer. The RF receiver further includes a programmable gain amplifier (PGA) having an input resistance that generates noise, where the PGA is driven by an output of the passive filter, and the noise generated by the input resistance of the PGA is suppressed.Type: ApplicationFiled: May 31, 2017Publication date: December 6, 2018Inventors: Navin Harwalkar, Arup Mukherji, John M. Khoury
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Patent number: 10141971Abstract: Embodiments of transceiver circuits disclosed herein include a first amplifier coupled to receive signals from an antenna during a receive (RX) mode of the transceiver circuit, a second amplifier coupled to transmit signals to the antenna during a transmit (TX) mode of the transceiver circuit, and a single impedance matching network coupled to the antenna and directly connected to a shared node to which the first and second amplifiers are directly connected. The single impedance matching network is configured to transform an impedance of the antenna into a resistance at the shared node. A control circuit is coupled to control the impedance transformation of the single impedance matching network, so as to provide a first resistance at the shared node during RX mode and a second resistance at the shared node during TX mode, wherein the second resistance is different from the first resistance.Type: GrantFiled: November 17, 2017Date of Patent: November 27, 2018Assignee: Silicon Laboratories Inc.Inventors: Mohamed Elkholy, Ayman Shafik, Yang Gao, Arup Mukherji, Navin Harwalkar
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Patent number: 10063203Abstract: Embodiments of power detector circuits and related methods to compensate for undesired DC offsets generated within power detector circuits are disclosed. Input signals having input frequencies are received and converted to a magnitude signal, and reference signals are also generated. The magnitude signal may include a DC component proportional to a power of the input signal along with undesired DC offsets. The reference signal may include a DC component proportional to a power of at least one input reference signal along with undesired DC offsets. To compensate for errors introduced by the DC offsets, a DC offset calibration signal or a gain are determined in a calibration mode and then applied in a normal mode to compensate for the DC offsets. For the calibration mode, a difference between the magnitude signal and the reference signal is compared to a threshold value to generate a power detection output signal.Type: GrantFiled: September 7, 2017Date of Patent: August 28, 2018Assignee: Silicon Laboratories Inc.Inventors: Navin Harwalkar, John M. Khoury
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Patent number: 9960756Abstract: Bypass techniques are provided herein to protect noise sensitive circuits from both internal and external noise sources. According to one embodiment, an integrated circuit (IC) chip may include a noise sensitive circuit coupled between a power supply pad and a first ground pad of the IC chip. In order to protect the first ground pad of the noise sensitive circuit, two distinct bypass paths are provided to route noise current around the noise sensitive circuit. Each bypass path terminates in its own ground pad (e.g., a second ground pad and third ground pad), which is separate from the first ground pad of the noise sensitive circuit.Type: GrantFiled: December 2, 2016Date of Patent: May 1, 2018Assignee: Silicon Laboratories Inc.Inventor: Navin Harwalkar
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Publication number: 20180054337Abstract: In one aspect, an apparatus includes: a mixer to receive a radio frequency (RF) signal and downconvert the RF signal into a second frequency signal; an amplifier coupled to the mixer to amplify the second frequency signal; an image rejection (IR) circuit coupled to the programmable gain amplifier (PGA) to orthogonally correct a gain and a phase of the amplified second frequency signal to output a corrected amplified second frequency signal; and a complex filter to filter the corrected amplified second frequency signal.Type: ApplicationFiled: October 31, 2017Publication date: February 22, 2018Inventors: John M. Khoury, Navin Harwalkar
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Patent number: 9819524Abstract: In one aspect, an apparatus includes: a mixer to receive a radio frequency (RF) signal and downconvert the RF signal into a second frequency signal; an amplifier coupled to the mixer to amplify the second frequency signal; an image rejection (IR) circuit coupled to the programmable gain amplifier (PGA) to orthogonally correct a gain and a phase of the amplified second frequency signal to output a corrected amplified second frequency signal; and a complex filter to filter the corrected amplified second frequency signal.Type: GrantFiled: November 21, 2014Date of Patent: November 14, 2017Assignee: Silicon Laboratories Inc.Inventors: John M. Khoury, Navin Harwalkar
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Publication number: 20160149604Abstract: In one aspect, an apparatus includes: a mixer to receive a radio frequency (RF) signal and downconvert the RF signal into a second frequency signal; an amplifier coupled to the mixer to amplify the second frequency signal; an image rejection (IR) circuit coupled to the programmable gain amplifier (PGA) to orthogonally correct a gain and a phase of the amplified second frequency signal to output a corrected amplified second frequency signal; and a complex filter to filter the corrected amplified second frequency signal.Type: ApplicationFiled: November 21, 2014Publication date: May 26, 2016Inventors: John M. Khoury, Navin Harwalkar
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Patent number: 9190975Abstract: A radio receiver and method of operating the same are disclosed. In one embodiment, the radio receiver may include a RF receive path configured to convey a first radio signal within a first band to a radio tuning circuit. The RF receive path may be controllable using a first AGC circuit. The radio receiver may also include a loop-through path configured to convey a second radio signal within a second band between an input and an output of the radio receiver. The second band may be different from the first band. The loop-through path may be controllable using a second AGC circuit.Type: GrantFiled: September 27, 2013Date of Patent: November 17, 2015Assignee: Silicon Laboratories Inc.Inventors: Dan B. Kasha, Russell Croman, Mike R. May, Mark W. May, Navin Harwalkar, Tim Stroud
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Patent number: 9178549Abstract: A radio frequency (RF) receiver front end includes an RF attenuator for receiving an RF input signal and a low noise amplifier (LNA). In one form, the LNA provides a differential output signal and includes a first polarity amplifier and a plurality of second polarity amplifiers. The first polarity amplifier has an input terminal coupled to the output of the RF attenuator, an output terminal for providing a first component of the differential RF output signal, and has a first input impedance. Each of the plurality of second polarity amplifiers has an input terminal coupled to the output of said RF attenuator, and an output terminal. The output terminals of said plurality of second polarity amplifiers are coupled together and form a second component of the differential RF output signal. Each of the plurality of second polarity amplifiers has a second input impedance higher than the first input impedance.Type: GrantFiled: October 18, 2013Date of Patent: November 3, 2015Assignee: SILICON LABORATORIES INC.Inventors: Navin Harwalkar, Tim Stroud, Dan Kasha
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Patent number: 9154084Abstract: An apparatus includes an integrated circuit. The integrated circuit includes a low-noise amplifier having a first complex input impedance. The integrated circuit includes a complex attenuator coupled to an input terminal of the integrated circuit. The complex attenuator has a second complex input impedance and a first complex output impedance. The apparatus may include a matching network coupled to the input terminal of the integrated circuit. The matching network is external to the integrated circuit. The matching network may have a first real input impedance and a second complex output impedance. The second complex output impedance is matched to the second complex input impedance.Type: GrantFiled: July 30, 2013Date of Patent: October 6, 2015Assignee: Silicon Laboratories Inc.Inventors: Navin Harwalkar, Dan B. Kasha
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Publication number: 20150111514Abstract: A radio frequency (RF) receiver front end includes an RF attenuator for receiving an RF input signal and a low noise amplifier (LNA). In one form, the LNA provides a differential output signal and includes a first polarity amplifier and a plurality of second polarity amplifiers. The first polarity amplifier has an input terminal coupled to the output of the RF attenuator, an output terminal for providing a first component of the differential RF output signal, and has a first input impedance. Each of the plurality of second polarity amplifiers has an input terminal coupled to the output of said RF attenuator, and an output terminal. The output terminals of said plurality of second polarity amplifiers are coupled together and form a second component of the differential RF output signal. Each of the plurality of second polarity amplifiers has a second input impedance higher than the first input impedance.Type: ApplicationFiled: October 18, 2013Publication date: April 23, 2015Applicant: Silicon Laboratories Inc.Inventors: Navin Harwalkar, Tim Stroud, Dan Kasha
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Publication number: 20150094007Abstract: A radio receiver and method of operating the same are disclosed. In one embodiment, the radio receiver may include a RF receive path configured to convey a first radio signal within a first band to a radio tuning circuit. The RF receive path may be controllable using a first AGC circuit. The radio receiver may also include a loop-through path configured to convey a second radio signal within a second band between an input and an output of the radio receiver. The second band may be different from the first band. The loop-through path may be controllable using a second AGC circuit.Type: ApplicationFiled: September 27, 2013Publication date: April 2, 2015Applicant: SILICON LABORATORIES INC.Inventors: Dan B. Kasha, Russell Croman, Mike R. May, Mark W. May, Navin Harwalkar, Tim Stroud
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Publication number: 20150035595Abstract: An apparatus includes an integrated circuit. The integrated circuit includes a low-noise amplifier having a first complex input impedance. The integrated circuit includes a complex attenuator coupled to an input terminal of the integrated circuit. The complex attenuator has a second complex input impedance and a first complex output impedance. The apparatus may include a matching network coupled to the input terminal of the integrated circuit. The matching network is external to the integrated circuit. The matching network may have a first real input impedance and a second complex output impedance. The second complex output impedance is matched to the second complex input impedance.Type: ApplicationFiled: July 30, 2013Publication date: February 5, 2015Applicant: Silicon Laboratories Inc.Inventors: Navin Harwalkar, Dan B. Kasha
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Patent number: 8035445Abstract: An embodiment of the present invention provides a system comprising a summing device and first amplifier portion. The summing device is coupled to an output node. The first amplifier portion is coupled between an input node and the summing device. The first amplifier portion includes a first amplifier, a first filter, and first and second switches. The first amplifier is coupled between the input node and the summing device on a first path. The first filter is coupled between the input node and the first amplifier on a second path, the second path being in parallel to the first path. The first switch is coupled between the input node and the first amplifier along the first path. The second switch is coupled between the input node and the first filter along the second path.Type: GrantFiled: July 30, 2010Date of Patent: October 11, 2011Assignee: Broadcom CorporationInventors: Ramon A. Gomez, Navin Harwalkar, Bryan Juo-Jung Hung, Francesco Gatta
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Publication number: 20110193626Abstract: An embodiment of the present invention provides a system comprising a summing device and first amplifier portion. The summing device is coupled to an output node. The first amplifier portion is coupled between an input node and the summing device. The first amplifier portion includes a first amplifier, a first filter, and first and second switches. The first amplifier is coupled between the input node and the summing device on a first path. The first filter is coupled between the input node and the first amplifier on a second path, the second path being in parallel to the first path. The first switch is coupled between the input node and the first amplifier along the first path. The second switch is coupled between the input node and the first filter along the second path.Type: ApplicationFiled: July 30, 2010Publication date: August 11, 2011Applicant: Broadcom CorporationInventors: Ramon A. Gomez, Navin Harwalkar, Bryan Juo-Jung Hung, Francesco Gatta