Abstract: A method and apparatus for a memory control system is provided. The memory control system includes a first memory controller designed to access and refresh a DRAM, using a clock, during a first operation mode. The memory control system further includes a second memory controller designed to maintain the DRAM during a second operation mode and to exit from the second operation mode. During the second operation mode a clock or the clock and power is turned off to the first memory controller, and upon returning to the first operation mode, no initialization of the first memory controller is needed. Since a significant proportion of the power is consumed by the first memory controller, power savings results from employing this technique.