Patents by Inventor Navin Monteiro

Navin Monteiro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Reducing power consumption in a sequential cache
    Patent number: 7457917
    Abstract: In one embodiment, the present invention includes a cache memory, which may be a sequential cache, having multiple banks. Each of the banks includes a data array, a decoder coupled to the data array to select a set of the data array, and a sense amplifier. Only a bank to be accessed may be powered, and in some embodiments early way information may be used to maintain remaining banks in a power reduced state. In some embodiments, clock gating may be used to maintain various components of the cache memory in a power reduced state. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 29, 2004
    Date of Patent: November 25, 2008
    Assignee: Intel Corporation
    Inventors: Satish Damaraju, Subramaniam Maiyuran, Peter Smith, Navin Monteiro
  • Reducing power consumption in a sequential cache
    Publication number: 20060143382
    Abstract: In one embodiment, the present invention includes a cache memory, which may be a sequential cache, having multiple banks. Each of the banks includes a data array, a decoder coupled to the data array to select a set of the data array, and a sense amplifier. Only a bank to be accessed may be powered, and in some embodiments early way information may be used to maintain remaining banks in a power reduced state. In some embodiments, clock gating may be used to maintain various components of the cache memory in a power reduced state. Other embodiments are described and claimed.
    Type: Application
    Filed: December 29, 2004
    Publication date: June 29, 2006
    Inventors: Satish Damaraju, Subramaniam Maiyuran, Peter Smith, Navin Monteiro