Patents by Inventor Navindra Navaratnam
Navindra Navaratnam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240128963Abstract: Systems or methods of the present disclosure may provide protection to gate-driving circuitry from anomalous electrical conditions. A method may include detecting an anomalous electrical condition at an input/output (I/O) terminal of an electrical component. The method may also include determining whether the anomalous electrical condition comprises an undershoot condition or an overshoot condition. Additionally, the method may include generating a bias voltage based on the determination that the anomalous electrical condition comprises the undershoot condition or the overshoot condition and applying the bias voltage to the I/O terminal of the electrical component.Type: ApplicationFiled: December 28, 2023Publication date: April 18, 2024Inventors: Navindra Navaratnam, Seh Leong Goh
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Patent number: 11183226Abstract: An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.Type: GrantFiled: November 30, 2020Date of Patent: November 23, 2021Assignee: Intel CorporationInventors: Navindra Navaratnam, Nasser A. Kurd, Bee Min Teng, Raymond Chong, Nasirul I. Chowdhury, Ali M. El-Husseini
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Publication number: 20210082481Abstract: An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.Type: ApplicationFiled: November 30, 2020Publication date: March 18, 2021Applicant: Intel CorporationInventors: Navindra Navaratnam, Nasser A. Kurd, Bee Min Teng, Raymond Chong, Nasirul I. Chowdhury, Ali M. El-Husseini
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Patent number: 10854249Abstract: An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.Type: GrantFiled: June 27, 2020Date of Patent: December 1, 2020Assignee: Intel CorporationInventors: Navindra Navaratnam, Nasser A. Kurd, Bee Min Teng, Raymond Chong, Nasirul I. Chowdhury, Ali M. El-Husseini
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Publication number: 20200327914Abstract: An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.Type: ApplicationFiled: June 27, 2020Publication date: October 15, 2020Applicant: Intel CorporationInventors: Navindra Navaratnam, Nasser A. Kurd, Bee Min Teng, Raymond Chong, Nasirul I. Chowdhury, Ali M. El-Husseini
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Patent number: 10706900Abstract: An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.Type: GrantFiled: November 1, 2018Date of Patent: July 7, 2020Assignee: Intel CorporationInventors: Navindra Navaratnam, Nasser A. Kurd, Bee Min Teng, Raymond Chong, Nasirul I. Chowdhury, Ali M. El-Husseini
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Publication number: 20200143853Abstract: An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.Type: ApplicationFiled: November 1, 2018Publication date: May 7, 2020Applicant: Intel CorporationInventors: Navindra Navaratnam, Nasser A. Kurd, Bee Min Teng, Raymond Chong, Nasirul I. Chowdhury, Ali M. El-Husseini
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Patent number: 10361705Abstract: An apparatus is provided which comprises: a receiver to receive a differential clock; a delay locked loop (DLL) coupled to the receiver; a first phase interpolator (PI) coupled to the DLL, the first PI to provide a first clock phase; a second PI coupled to the DLL, wherein the second PI is to provide a second or third clock phase; circuitry to adjust the first and second PIs according to the first clock phase, and the second or third clock phase.Type: GrantFiled: June 12, 2018Date of Patent: July 23, 2019Assignee: Intel CorporationInventors: Chenchu Punnarao Bandi, Amit Kumar Srivastava, Navindra Navaratnam
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Publication number: 20190007054Abstract: An apparatus is provided which comprises: a receiver to receive a differential clock; a delay locked loop (DLL) coupled to the receiver; a first phase interpolator (PI) coupled to the DLL, the first PI to provide a first clock phase; a second PI coupled to the DLL, wherein the second PI is to provide a second or third clock phase; circuitry to adjust the first and second PIs according to the first clock phase, and the second or third clock phase.Type: ApplicationFiled: June 12, 2018Publication date: January 3, 2019Applicant: Intel CorporationInventors: Chenchu Punnarao Bandi, Amit Kumar Srivastava, Navindra Navaratnam
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Patent number: 8929157Abstract: Circuitry to provide a supply voltage. A voltage regulator is coupled to receive a target reference signal. The voltage regulator generates a supply voltage (Vtt) and is coupled to receive the supply voltage as an input signal. An upper limit comparator receives an upper limit voltage signal that is higher than the target reference voltage signal and the supply voltage to generate a “too high” signal when the supply voltage exceeds an upper threshold. A lower limit comparator receives a lower limit voltage signal that is lower than the target reference voltage signal and the supply voltage to generate a “too low” signal when the supply voltage is below a lower threshold. A pull up current source is coupled to pull the supply voltage up in response to the too low signal. A pull down current source is coupled to pull the supply voltage down in response to the too high signal.Type: GrantFiled: November 19, 2012Date of Patent: January 6, 2015Assignee: Intel CorporationInventors: Christopher P. Mozak, Navindra Navaratnam, Mahmoud Elassal
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Publication number: 20140140146Abstract: Circuitry to provide a supply voltage. A voltage regulator is coupled to receive a target reference signal. The voltage regulator generates a supply voltage (Vtt) and is coupled to receive the supply voltage as an input signal. An upper limit comparator receives an upper limit voltage signal that is higher than the target reference voltage signal and the supply voltage to generate a “too high” signal when the supply voltage exceeds an upper threshold. A lower limit comparator receives a lower limit voltage signal that is lower than the target reference voltage signal and the supply voltage to generate a “too low” signal when the supply voltage is below a lower threshold. A pull up current source is coupled to pull the supply voltage up in response to the too low signal. A pull down current source is coupled to pull the supply voltage down in response to the too high signal.Type: ApplicationFiled: November 19, 2012Publication date: May 22, 2014Inventors: CHRISTOPHER P. MOZAK, NAVINDRA NAVARATNAM, MAHMOUD ELASSAL
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Publication number: 20090248945Abstract: In some embodiments, a circuit is provided with a transmitter to generate switching noise during clock events when no transition occurs to reduce data dependent switching noise.Type: ApplicationFiled: March 31, 2008Publication date: October 1, 2009Inventors: Navindra Navaratnam, Edward Burton, Mahadev Nemani, Yanmei Tian, Harry Muljono
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Patent number: 7590392Abstract: In some embodiments, a chip with a transmitter having a transmitter driver is provided. Also provided is a general compensation circuit coupled to the transmitter to generally compensate the transmitter driver and a specific compensation circuit coupled to the transmitter driver to specifically compensate the transmitter driver. Other embodiments are disclosed and claimed herein.Type: GrantFiled: October 31, 2005Date of Patent: September 15, 2009Assignee: Intel CorporationInventors: Navindra Navaratnam, Aninda K. Roy
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Patent number: 7429881Abstract: According to embodiments of the subject matter disclosed in this application, a wide input common mode sense amplifier may include a level shifter stage and an amplifier stage. The level shifter comprises a CMOS differential amplifier that has a rail-to-rail input common mode range. The level shifter accepts two input signals with a common mode voltage in a rail-to-rail range and produces two output signals with a stable common mode voltage. The differential amplifier amplifies the two output signals from the level shifter stage with high gain. The disclosed sense amplifier may be used to measure delay between two discrete time events.Type: GrantFiled: January 6, 2006Date of Patent: September 30, 2008Assignee: Intel CorporationInventors: Chaodan Deng, Songmin Kim, Navindra Navaratnam
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Publication number: 20070159215Abstract: According to embodiments of the subject matter disclosed in this application, a wide input common mode sense amplifier may include a level shifter stage and an amplifier stage. The level shifter comprises a CMOS differential amplifier that has a rail-to-rail input common mode range. The level shifter accepts two input signals with a common mode voltage in a rail-to-rail range and produces two output signals with a stable common mode voltage. The differential amplifier amplifies the two output signals from the level shifter stage with high gain. The disclosed sense amplifier may be used to measure delay between two discrete time events.Type: ApplicationFiled: January 6, 2006Publication date: July 12, 2007Inventors: Chaodan Deng, Songmin Kim, Navindra Navaratnam
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Publication number: 20070099572Abstract: In some embodiments, a chip with a transmitter having a transmitter driver is provided. Also provided is a general compensation circuit coupled to the transmitter to generally compensate the transmitter driver and a specific compensation circuit coupled to the transmitter driver to specifically compensate the transmitter driver. Other embodiments are disclosed and claimed herein.Type: ApplicationFiled: October 31, 2005Publication date: May 3, 2007Inventors: Navindra Navaratnam, Aninda Roy
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Patent number: 7038513Abstract: A system and method for processing signals determines rise and fall times of a driving signal, compares the rise and fall times to desired values, and independently controls the rise and fall times to equal the desired values. The rise and fall times may be controlled by generating one or more first correction bits based on a difference between the rise time and a corresponding one of the desired values, generating one or more second correction bits based on a difference between the fall time and a corresponding one of the desired values, and then separately applying the bits to independently control the rise and fall times of the driving signal. The driving signal may be an I/O signal or another type of signal.Type: GrantFiled: June 29, 2004Date of Patent: May 2, 2006Assignee: Intel CorporationInventors: Timothy M. Wilson, Michael C. Rifani, Songmin Kim, Greg Taylor, Navindra Navaratnam
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Publication number: 20050285648Abstract: A system and method for processing signals determines rise and fall times of a driving signal, compares the rise and fall times to desired values, and independently controls the rise and fall times to equal the desired values. The rise and fall times may be controlled by generating one or more first correction bits based on a difference between the rise time and a corresponding one of the desired values, generating one or more second correction bits based on a difference between the fall time and a corresponding one of the desired values, and then separately applying the bits to independently control the rise and fall times of the driving signal. The driving signal may be an I/O signal or another type of signal.Type: ApplicationFiled: June 29, 2004Publication date: December 29, 2005Inventors: Timothy Wilson, Michael Rifani, Songmin Kim, Greg Taylor, Navindra Navaratnam