Abstract: A semiconductor device package having pre-formed and placed through vias and a process for making such a package is provided. One or more signal conduits are placed in a holder that is subsequently embedded in an encapsulated semiconductor device package. The ends of the signal conduits are exposed and the signal conduits are then used as through package vias, providing signal-bearing pathways between interconnects or contacts on the bottom and top of the package. Holders can be provided in a variety of geometries and materials, depending upon the nature of the application. Further, multiple holders with signal conduits can be provided in a single package to provide for more complex interconnect configuration demands in, for example, system-in-a-package applications.

Abstract: A semiconductor device package having pre-formed and placed through vias and a process for making such a package is provided. One or more signal conduits are coupled to a lead frame that is subsequently embedded in an encapsulated semiconductor device package. The free end of signal conduits is exposed while the other end remains coupled to a lead frame. The signal conduits are then used as through package vias, providing signal-bearing pathways between interconnects or contacts on the bottom and top of the package and the leads.

Abstract: A method for forming through vias in a semiconductor device package prior to package encapsulation is provided. One or more signal conduits are formed through photolithography and metal deposition on a printed circuit substrate having interconnect pads. After removing photoresistive material, the semiconductor device package is built by encapsulating the signal conduits along with any semiconductor die, wire bonding, and other parts of the package. Free ends of each signal conduit are exposed and the signal conduits are used as through vias to provide signal-bearing pathways between connections from a top-mounted package to a printed circuit substrate interconnect and electrical contacts of the semiconductor die or package contacts. Using this method, signal conduits can be provided in a variety of geometric placings on the printed circuit substrate for inclusion in a semiconductor device package. A semiconductor device package incorporating the pre-fabricated through vias is also provided.

Abstract: A method for forming through vias in a semiconductor device package prior to package encapsulation is provided. One or more signal conduits are formed through photolithography and metal deposition on a printed circuit substrate having interconnect pads. After removing photoresistive material, the semiconductor device package is built by encapsulating the signal conduits along with any semiconductor die, wire bonding, and other parts of the package. Free ends of each signal conduit are exposed and the signal conduits are used as through vias to provide signal-bearing pathways between connections from a top-mounted package to a printed circuit substrate interconnect and electrical contacts of the semiconductor die or package contacts. Using this method, signal conduits can be provided in a variety of geometric placings on the printed circuit substrate for inclusion in a semiconductor device package. A semiconductor device package incorporating the pre-fabricated through vias is also provided.

Abstract: A semiconductor device package having pre-formed and placed through vias and a process for making such a package is provided. One or more signal conduits are coupled to a lead frame that is subsequently embedded in an encapsulated semiconductor device package. The free end of signal conduits is exposed while the other end remains coupled to a lead frame. The signal conduits are then used as through package vias, providing signal-bearing pathways between interconnects or contacts on the bottom and top of the package and the leads.

Abstract: A semiconductor device package having pre-formed and placed through vias and a process for making such a package is provided. One or more signal conduits are placed in a holder that is subsequently embedded in an encapsulated semiconductor device package. The ends of the signal conduits are exposed and the signal conduits are then used as through package vias, providing signal-bearing pathways between interconnects or contacts on the bottom and top of the package. Holders can be provided in a variety of geometries and materials, depending upon the nature of the application. Further, multiple holders with signal conduits can be provided in a single package to provide for more complex interconnect configuration demands in, for example, system-in-a-package applications.

Abstract: A method for forming signal conduits before encapsulation for incorporation as through vias in a semiconductor device package is provided. One or more signal conduits are formed through photolithography and metal deposition on a metal film or substrate. After removing photoresistive material, the semiconductor device package is built by encapsulating the signal conduits along with any semiconductor die and other parts of the package. The ends of the signal conduits are exposed and the signal conduits can then be used as through vias, providing signal-bearing pathways between interconnects or contacts on the bottom and top of the package, and electrical contacts of the semiconductor die. Using this method, signal conduits can be provided in a variety of geometric placings in the semiconductor device package. A semiconductor device package including the signal conduits made from the above method is also provided.

Abstract: The present invention discloses an on chip decoupling capacitor structure having a first decoupling capacitor with one electrode formed in the conductively doped silicon substrate and a second electrode made of conductively doped polysilicon. The second electrode is a common electrode to a second decoupling capacitor overlying and thereby coupled in parallel to said first decoupling capacitor. The second capacitor's first electrode is the common electrode and its second electrode is made of conductively doped polysilicon. The electrodes made of the conductively doped polysilicon may be further enhanced by forming a silicided material, such as tungsten silicide, thereon. The decoupling capacitors' dielectric can be formed from high dielectric constant materials, such as TEOS, oxide, nitride or any combination thereof.

Abstract: Disclosed is a baffle apparatus for insertion into a semiconductor wafer processing furnace to diffuse processing gases that are injected into the furnace by an injector nozzle. The baffle apparatus comprises:a diffuser plate assembly having an upper end and a lower end, the diffuser plate assembly having at least one diffuser plate against which injected gases are to be forced; andthe lower end of the diffuser plate assembly being sized and shaped to engage with and be supported by an elongated wafer paddle.

Abstract: In the present invention, a stable and uniform texturized surface of a conductive structure is developed by annealing, oxidizing and etching a layer of metal silicide that has been deposited over a semiconductive material. Using this process during fabrication of memory cell in a DRAM will increase storage node capacitance by creating texturized capacitor cell plates that will retain their textured surfaces throughout implementation of conventional DRAM fabrication processes.

Abstract: A mini-stack capacitor process, developed for DRAM fabrication, is used to create a stacked capacitor by depositing multiple layers of dielectric over existing digit and word lines. The exposed top dielectric is then masked and etched away between two adjacent digit lines, the resist is stripped and subsequent etches (or etch) remove(s) the remaining dielectric layers thereby exposing the underlying conductively doped diffusion region. The storage node poly is then deposited and patterned, followed by subsequent depositions of a cell dielectric and cell plate poly. The selection of the number of dielectrics used and the type and/or sequence of dielectric etches used are the crux of the invention that substantially increases the surface area of a given stacked capacitor by approximately 40 to 80%.

Abstract: Disclosed is a baffle apparatus for insertion into a semiconductor wafer processing furnace to diffuse processing gases that are injected into the furnace by an injector nozzle. The baffle apparatus comprises: a diffuser plate assembly having an upper end and a lower end, the diffuser plate assembly having at least one diffuser plate against which injected gases are to be forced; and the lower end of the diffuser plate assembly being sized and shaped to engage with and be supported by an elongated wafer paddle.

Abstract: An apparatus used to HF gas etch a plurality of integrated circuit wafers within an etch chamber, followed by a de-ionized water cascade rinse in the chamber. On completion of the rinse and removal of the wafer carriers, the apparatus, housing, and supply conduits are purged with an inert gas to prepare the apparatus for a next batch of wafer carriers. The apparatus includes process-control means for automatically controlling each step of the process.

Abstract: A process for forming silicon dioxide, SiO.sub.2, or silicon nitride, Si.sub.3 N.sub.4, layers on selected substrates which includes reacting diethylsilane, C.sub.4 H.sub.12 Si, with a selected oxygen-containing compound or nitrogen-containing compound in a plasma enhanced chemical vapor deposition (PECVD) chamber. The conformality of the coatings thus formed is in the range of 85% to 98%. The diethylsilane liquid source for the associated gas flow processing system may be maintained and operated at a source temperature as low as room temperature.

Abstract: Disclosed is a semiconductor processing furnace flow restricting apparatus for insertion into a longitudinally elongated semiconductor wafer processing furnace to create back pressure to increase residence time of processing gases within the furnace. The apparatus comprises:at least two ring-like members, one of the ring-like members being concentrically mounted inside the other, the ring-like members each having a fore longitudinal end and an aft longitudinal end, the two ring-like members each having a varying diameter which tapers inwardly from the fore longitudinal end to the aft longitudinal end; anda lower mounting assembly having a male fitting cross sectional size and shape which is complementary to an upward female size and shape of the elongated wafer paddle, the male shape of the mounting assembly being supportable within the female shape of the wafer paddle to laterally position the two rings when the paddle and apparatus are received within a semiconductor wafer processing furnace.

Abstract: Disclosed is a quartz tube for a furnace for processing semiconductor wafers. The furnace comprises:an elongated hollow body having opposed first and second ends and a longitudinal axis;an injector opening being formed in the first end, the injector opening including sidewalls which are spaced to slidably receive an elongated gas injector assembly through the opening; andan alignment jig received within the hollow body inwardly adjacent the first end and injector opening, the alignment jig including support means for engaging and aligning a gas injector with the injector opening to support a gas injector to emit gas substantially along the longitudinal tube body axis.

Abstract: An R-F electrode apparatus is provided featuring self-adjusting, spring biased electrodes, removably attached to a removable substrate holder, within a chamber used for plasma reactive treatment processes, particularly those involving semiconductor wafers. The apparatus further features base electrodes shaped and supported to insure uniform transmission of electrical energy during operation. The apparatus also provides an automatic means for wiping, self-cleaning action between the contact surfaces of opposing electrodes during introduction and removal of the substrate holder from the reaction chamber. The base electrodes are removably attached to standard electrical feedthroughs located in the reaction chamber wall, which lead to an external R-F power supply.