Patents by Inventor Navneet K. Singh
Navneet K. Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240405459Abstract: According to the various aspects, the present disclosure is directed to printed circuit board assemblies having a plurality of printed circuit board units or modules that use board connectors for joining the printed circuit board units. In an aspect, the board connector has a first surface, which may be a top surface, and an opposing second surface, which may be a bottom surface, and a plurality of openings, including a first set of connector openings for providing electrical connections between the at least two plurality of printed circuit board units. In another aspect, a method that includes forming a first printed circuit board unit with a first connecting portion and a second printed circuit board unit with a second connecting portion, and the first and second connecting are electrically coupled with the printed circuit board connector.Type: ApplicationFiled: June 1, 2023Publication date: December 5, 2024Inventors: Navneet K. SINGH, Aiswarya PIOUS, Samarth ALVA, Sharvil DESAI, Ralph JENSEN, Carlos MARISCAL, Michael CROCKER, Kevin MA, Pedro Jose MARTINEZ NARVAEZ
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Publication number: 20220015273Abstract: An example electronic device is disclosed that includes a printed circuit board, an electronic component coupled to the printed circuit board, and a solderless shield coupled to the printed circuit board and covering the electronic component.Type: ApplicationFiled: September 23, 2021Publication date: January 13, 2022Inventors: Bala P. Subramanya, Prakash Kurma Raju, Navneet K. Singh, Sachin Bedare, Vijith Halestoph R.
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Patent number: 10734393Abstract: Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include attaching a die on a board, attaching a substrate on the die, wherein the substrate comprises a first region and a peripheral region, attaching a first memory device on the central region of the substrate, and attaching at least one additional memory device on the peripheral region of the substrate, wherein the at least one additional memory device is not disposed over the die.Type: GrantFiled: November 7, 2018Date of Patent: August 4, 2020Assignee: Intel CorporationInventors: Navneet K. Singh, Shanto A. Thomas, Ranjul Balakrishnan
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Patent number: 10720407Abstract: A microelectronic interposer for a microelectronic package may be fabricated, wherein a first microelectronic device within the microelectronic package is in electronic communication with at least one second microelectronic device through the microelectronic interposer which positions the at least one second microelectronic device outside a periphery of the first microelectronic device. The microelectronic interposer may further include at least one recess for achieving a desired height and/or enabling various configurations for the microelectronic package.Type: GrantFiled: December 5, 2018Date of Patent: July 21, 2020Assignee: Intel CorporationInventors: Navneet K. Singh, Ranjul Balakrishnan
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Patent number: 10656177Abstract: A system includes a probe connector including first traces coupled to first conductors curvilinearly arranged around a first elongated portion of the probe connector. The system further includes a circuit board including second traces coupled to first connector pads curvilinearly arranged around a first hole in the circuit board. The first connector pads are to couple to the first conductors of the probe connector when the first elongated portion is inserted in the first hole. The system further comprises a first integrated circuit disposed on the circuit board, the first integrated circuit being coupled to the second traces.Type: GrantFiled: May 13, 2019Date of Patent: May 19, 2020Assignee: Intel CorporationInventors: Vikas Rao, Navneet K. Singh, Naveen G
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Publication number: 20190271720Abstract: A system includes a probe connector including first traces coupled to first conductors curvilinearly arranged around a first elongated portion of the probe connector. The system further includes a circuit board including second traces coupled to first connector pads curvilinearly arranged around a first hole in the circuit board. The first connector pads are to couple to the first conductors of the probe connector when the first elongated portion is inserted in the first hole. The system further comprises a first integrated circuit disposed on the circuit board, the first integrated circuit being coupled to the second traces.Type: ApplicationFiled: May 13, 2019Publication date: September 5, 2019Inventors: Vikas Rao, Navneet K. Singh, Naveen G
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Publication number: 20190206839Abstract: Electronic device package technology is disclosed. An electronic device package in accordance with the present disclosure can include a heat spreader disposed between an electronic component and an electronic device. The heat spreader can be in thermal communication with the electronic component and operable to transfer heat from the electronic component to a lateral location beyond a first peripheral portion of the electronic component. Associated systems and methods are also disclosed.Type: ApplicationFiled: December 29, 2017Publication date: July 4, 2019Applicant: Intel CorporationInventors: Ranjul Balakrishnan, Navneet K. Singh, Bijendra Singh
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Patent number: 10317428Abstract: Disclosed herein is technology of a probe connector for a probing pad structure around a thermal attach mounting hole. A probe connector includes a socket frame including a first channel and an elongated body including a second channel. Socket conductors are disposed in the socket frame around the first channel. The second channel is disposed at a first distal end of the elongated body, and the elongated body is disposed on the socket frame. The socket conductors are to make electrical contact with a probing pad structure disposed on a surface area around a thermal attach mounting hole of a circuit board in response to a loading attachment engaging with the elongated body via the second channel, the socket frame via the first channel, and the circuit board via the thermal attach mounting hole.Type: GrantFiled: November 2, 2016Date of Patent: June 11, 2019Assignee: Intel CorporationInventors: Vikas Rao, Navneet K. Singh, Naveen G
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Publication number: 20190109115Abstract: A microelectronic interposer for a microelectronic package may be fabricated, wherein a first microelectronic device within the microelectronic package is in electronic communication with at least one second microelectronic device through the microelectronic interposer which positions the at least one second microelectronic device outside a periphery of the first microelectronic device. The microelectronic interposer may further include at least one recess for achieving a desired height and/or enabling various configurations for the microelectronic package.Type: ApplicationFiled: December 5, 2018Publication date: April 11, 2019Applicant: Intel CorporationInventors: Navneet K. Singh, Ranjul Balakrishnan
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Publication number: 20190074281Abstract: Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include attaching a die on a board, attaching a substrate on the die, wherein the substrate comprises a first region and a peripheral region, attaching a first memory device on the central region of the substrate, and attaching at least one additional memory device on the peripheral region of the substrate, wherein the at least one additional memory device is not disposed over the die.Type: ApplicationFiled: November 7, 2018Publication date: March 7, 2019Applicant: Intel CorporationInventors: Navneet K. Singh, Shanto A. Thomas, Ranjul Balakrishnan
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Patent number: 10199353Abstract: A microelectronic interposer for a microelectronic package may be fabricated, wherein a first microelectronic device within the microelectronic package is in electronic communication with at least one second microelectronic device through the microelectronic interposer which positions the at least one second microelectronic device outside a periphery of the first microelectronic device. The microelectronic interposer may further include at least one recess for achieving a desired height and/or enabling various configurations for the microelectronic package.Type: GrantFiled: September 12, 2016Date of Patent: February 5, 2019Assignee: Intel CorporationInventors: Navneet K. Singh, Ranjul Balakrishnan
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Patent number: 10177161Abstract: Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include attaching a die on a board, attaching a substrate on the die, wherein the substrate comprises a first region and a peripheral region, attaching a first memory device on the central region of the substrate, and attaching at least one additional memory device on the peripheral region of the substrate, wherein the at least one additional memory device is not disposed over the die.Type: GrantFiled: December 28, 2016Date of Patent: January 8, 2019Assignee: Intel CorporationInventors: Navneet K. Singh, Shanto A. Thomas, Ranjul Balakrishnan
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Publication number: 20180182734Abstract: Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include attaching a die on a board, attaching a substrate on the die, wherein the substrate comprises a first region and a peripheral region, attaching a first memory device on the central region of the substrate, and attaching at least one additional memory device on the peripheral region of the substrate, wherein the at least one additional memory device is not disposed over the die.Type: ApplicationFiled: December 28, 2016Publication date: June 28, 2018Applicant: Intel CorporationInventors: Navneet K. Singh, Shanto A. Thomas, Ranjul Balakrishnan
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Publication number: 20180120347Abstract: Disclosed herein is technology of a probe connector for a probing pad structure around a thermal attach mounting hole. A probe connector includes a socket frame including a first channel and an elongated body including a second channel. Socket conductors are disposed in the socket frame around the first channel. The second channel is disposed at a first distal end of the elongated body, and the elongated body is disposed on the socket frame. The socket conductors are to make electrical contact with a probing pad structure disposed on a surface area around a thermal attach mounting hole of a circuit board in response to a loading attachment engaging with the elongated body via the second channel, the socket frame via the first channel, and the circuit board via the thermal attach mounting hole.Type: ApplicationFiled: November 2, 2016Publication date: May 3, 2018Inventors: Vikas Rao, Navneet K. Singh, Naveen G
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Publication number: 20180076171Abstract: A microelectronic interposer for a microelectronic package may be fabricated, wherein a first microelectronic device within the microelectronic package is in electronic communication with at least one second microelectronic device through the microelectronic interposer which positions the at least one second microelectronic device outside a periphery of the first microelectronic device. The microelectronic interposer may further include at least one recess for achieving a desired height and/or enabling various configurations for the microelectronic package.Type: ApplicationFiled: September 12, 2016Publication date: March 15, 2018Applicant: INTEL CORPORATIONInventors: Navneet K. Singh, Ranjul Balakrishnan