Patents by Inventor Navneet K. Singh

Navneet K. Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220015273
    Abstract: An example electronic device is disclosed that includes a printed circuit board, an electronic component coupled to the printed circuit board, and a solderless shield coupled to the printed circuit board and covering the electronic component.
    Type: Application
    Filed: September 23, 2021
    Publication date: January 13, 2022
    Inventors: Bala P. Subramanya, Prakash Kurma Raju, Navneet K. Singh, Sachin Bedare, Vijith Halestoph R.
  • Patent number: 10734393
    Abstract: Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include attaching a die on a board, attaching a substrate on the die, wherein the substrate comprises a first region and a peripheral region, attaching a first memory device on the central region of the substrate, and attaching at least one additional memory device on the peripheral region of the substrate, wherein the at least one additional memory device is not disposed over the die.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: August 4, 2020
    Assignee: Intel Corporation
    Inventors: Navneet K. Singh, Shanto A. Thomas, Ranjul Balakrishnan
  • Patent number: 10720407
    Abstract: A microelectronic interposer for a microelectronic package may be fabricated, wherein a first microelectronic device within the microelectronic package is in electronic communication with at least one second microelectronic device through the microelectronic interposer which positions the at least one second microelectronic device outside a periphery of the first microelectronic device. The microelectronic interposer may further include at least one recess for achieving a desired height and/or enabling various configurations for the microelectronic package.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: July 21, 2020
    Assignee: Intel Corporation
    Inventors: Navneet K. Singh, Ranjul Balakrishnan
  • Patent number: 10656177
    Abstract: A system includes a probe connector including first traces coupled to first conductors curvilinearly arranged around a first elongated portion of the probe connector. The system further includes a circuit board including second traces coupled to first connector pads curvilinearly arranged around a first hole in the circuit board. The first connector pads are to couple to the first conductors of the probe connector when the first elongated portion is inserted in the first hole. The system further comprises a first integrated circuit disposed on the circuit board, the first integrated circuit being coupled to the second traces.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: May 19, 2020
    Assignee: Intel Corporation
    Inventors: Vikas Rao, Navneet K. Singh, Naveen G
  • Publication number: 20190271720
    Abstract: A system includes a probe connector including first traces coupled to first conductors curvilinearly arranged around a first elongated portion of the probe connector. The system further includes a circuit board including second traces coupled to first connector pads curvilinearly arranged around a first hole in the circuit board. The first connector pads are to couple to the first conductors of the probe connector when the first elongated portion is inserted in the first hole. The system further comprises a first integrated circuit disposed on the circuit board, the first integrated circuit being coupled to the second traces.
    Type: Application
    Filed: May 13, 2019
    Publication date: September 5, 2019
    Inventors: Vikas Rao, Navneet K. Singh, Naveen G
  • Publication number: 20190206839
    Abstract: Electronic device package technology is disclosed. An electronic device package in accordance with the present disclosure can include a heat spreader disposed between an electronic component and an electronic device. The heat spreader can be in thermal communication with the electronic component and operable to transfer heat from the electronic component to a lateral location beyond a first peripheral portion of the electronic component. Associated systems and methods are also disclosed.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 4, 2019
    Applicant: Intel Corporation
    Inventors: Ranjul Balakrishnan, Navneet K. Singh, Bijendra Singh
  • Patent number: 10317428
    Abstract: Disclosed herein is technology of a probe connector for a probing pad structure around a thermal attach mounting hole. A probe connector includes a socket frame including a first channel and an elongated body including a second channel. Socket conductors are disposed in the socket frame around the first channel. The second channel is disposed at a first distal end of the elongated body, and the elongated body is disposed on the socket frame. The socket conductors are to make electrical contact with a probing pad structure disposed on a surface area around a thermal attach mounting hole of a circuit board in response to a loading attachment engaging with the elongated body via the second channel, the socket frame via the first channel, and the circuit board via the thermal attach mounting hole.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: June 11, 2019
    Assignee: Intel Corporation
    Inventors: Vikas Rao, Navneet K. Singh, Naveen G
  • Publication number: 20190109115
    Abstract: A microelectronic interposer for a microelectronic package may be fabricated, wherein a first microelectronic device within the microelectronic package is in electronic communication with at least one second microelectronic device through the microelectronic interposer which positions the at least one second microelectronic device outside a periphery of the first microelectronic device. The microelectronic interposer may further include at least one recess for achieving a desired height and/or enabling various configurations for the microelectronic package.
    Type: Application
    Filed: December 5, 2018
    Publication date: April 11, 2019
    Applicant: Intel Corporation
    Inventors: Navneet K. Singh, Ranjul Balakrishnan
  • Publication number: 20190074281
    Abstract: Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include attaching a die on a board, attaching a substrate on the die, wherein the substrate comprises a first region and a peripheral region, attaching a first memory device on the central region of the substrate, and attaching at least one additional memory device on the peripheral region of the substrate, wherein the at least one additional memory device is not disposed over the die.
    Type: Application
    Filed: November 7, 2018
    Publication date: March 7, 2019
    Applicant: Intel Corporation
    Inventors: Navneet K. Singh, Shanto A. Thomas, Ranjul Balakrishnan
  • Patent number: 10199353
    Abstract: A microelectronic interposer for a microelectronic package may be fabricated, wherein a first microelectronic device within the microelectronic package is in electronic communication with at least one second microelectronic device through the microelectronic interposer which positions the at least one second microelectronic device outside a periphery of the first microelectronic device. The microelectronic interposer may further include at least one recess for achieving a desired height and/or enabling various configurations for the microelectronic package.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: February 5, 2019
    Assignee: Intel Corporation
    Inventors: Navneet K. Singh, Ranjul Balakrishnan
  • Patent number: 10177161
    Abstract: Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include attaching a die on a board, attaching a substrate on the die, wherein the substrate comprises a first region and a peripheral region, attaching a first memory device on the central region of the substrate, and attaching at least one additional memory device on the peripheral region of the substrate, wherein the at least one additional memory device is not disposed over the die.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: January 8, 2019
    Assignee: Intel Corporation
    Inventors: Navneet K. Singh, Shanto A. Thomas, Ranjul Balakrishnan
  • Publication number: 20180182734
    Abstract: Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include attaching a die on a board, attaching a substrate on the die, wherein the substrate comprises a first region and a peripheral region, attaching a first memory device on the central region of the substrate, and attaching at least one additional memory device on the peripheral region of the substrate, wherein the at least one additional memory device is not disposed over the die.
    Type: Application
    Filed: December 28, 2016
    Publication date: June 28, 2018
    Applicant: Intel Corporation
    Inventors: Navneet K. Singh, Shanto A. Thomas, Ranjul Balakrishnan
  • Publication number: 20180120347
    Abstract: Disclosed herein is technology of a probe connector for a probing pad structure around a thermal attach mounting hole. A probe connector includes a socket frame including a first channel and an elongated body including a second channel. Socket conductors are disposed in the socket frame around the first channel. The second channel is disposed at a first distal end of the elongated body, and the elongated body is disposed on the socket frame. The socket conductors are to make electrical contact with a probing pad structure disposed on a surface area around a thermal attach mounting hole of a circuit board in response to a loading attachment engaging with the elongated body via the second channel, the socket frame via the first channel, and the circuit board via the thermal attach mounting hole.
    Type: Application
    Filed: November 2, 2016
    Publication date: May 3, 2018
    Inventors: Vikas Rao, Navneet K. Singh, Naveen G
  • Publication number: 20180076171
    Abstract: A microelectronic interposer for a microelectronic package may be fabricated, wherein a first microelectronic device within the microelectronic package is in electronic communication with at least one second microelectronic device through the microelectronic interposer which positions the at least one second microelectronic device outside a periphery of the first microelectronic device. The microelectronic interposer may further include at least one recess for achieving a desired height and/or enabling various configurations for the microelectronic package.
    Type: Application
    Filed: September 12, 2016
    Publication date: March 15, 2018
    Applicant: INTEL CORPORATION
    Inventors: Navneet K. Singh, Ranjul Balakrishnan