Abstract: Electronic design automation (EDA) systems, methods, and computer readable media are presented for adding design for test (DFT) logic at register transfer level (RTL) into an integrated circuit (IC) design at RTL. In some embodiments, the DFT logic at RTL includes a port that connects to a hierarchical reference with a hierarchical path in the tree structure hierarchy to a part of the IC design at RTL. Such DFT modification helps to decrease the number of new ports added at this stage, and as a result assists subsequent debugging and back-annotation of RTL.

Abstract: In one aspect, electronic design automation systems, methods, and non-transitory computer readable media are presented for adding a memory built-in self-test (MBIST) logic at register transfer level (RTL) or at netlist level into an integrated circuit (IC) design. In some embodiments, the MBIST logic is coupled to a physical memory module via a logical boundary of an intermediate level module that contains the physical memory module. The MBIST logic helps to keep intact integrity of the intermediate level module, making it more likely to meet any specified performance of the intermediate level module and reduce area overhead.

Abstract: Method and apparatus for testing the memory components of an integrated Circuit (IC) using a routing logic and a built-in design for test (DFT) hardware processing device. Based on input provided from an interface controller to the IC, the IC is tested according to one of at least two modes. In a first mode, the built-in DFT hardware processing device executes a test that checks for faults in the physical memory of the IC. In a second mode, the built-in DFT hardware processing device executes a test that checks for faults in the error correction logic of the IC. By using the same routing logic and built-in DFT hardware processing device, tests of the memory components according to the first and second mode can be executed on an automatic and serial basis, even after the manufacture of the IC.

Abstract: Aspects of the present disclosure involve insertion of power domain aware memory testing logic into integrated circuit designs to enable efficient testing of the memories embedded therein. In example embodiments, each power domain of the integrated circuit, and the memories included therein, are associated with dedicated test data register (TDR) set and instruction set. Each instruction set causes memory test logic circuitry in the integrated circuit to test the memories included in the corresponding power domain in parallel. Once testing of memories within a particular power domain is over, the test circuitry tests memories belonging to another power domain in parallel, and so on.

Abstract: Testing of memories is done using an optimized memory built-in-self-test (MBIST) approach, including the generation of compact models for memory. Cost functions are constructed from estimated parameters affecting MBIST, and a user is able to assign relative weights to the parameters. Estimated parameters include MBIST area, wiring congestion, and timing overhead, as well as power consumption and timing. The cost functions are minimized using optimization techniques, resulting in an optimized grouping of memory devices and an optimized schedule for MBIST testing. The estimated parameters may be derived from a compact model constructed from data experimentally-derived from various memory devices. This approach allows a circuit designer to generate and revise groupings and schedules prior to running a full design flow, saving time and cost, while still achieving high-quality results.

Abstract: Testing of memories is done using an optimized memory built-in-self-test (MBIST) approach, including the generation of compact models for memory. Cost functions are constructed from estimated parameters affecting MBIST, and a user is able to assign relative weights to the parameters. Estimated parameters include MBIST area, wiring congestion, and timing overhead, as well as power consumption and timing. The cost functions are minimized using optimization techniques, resulting in an optimized grouping of memory devices and an optimized schedule for MBIST testing. The estimated parameters may be derived from a compact model constructed from data experimentally-derived from various memory devices. This approach allows a circuit designer to generate and revise groupings and schedules prior to running a full design flow, saving time and cost, while still achieving high-quality results.

Abstract: Testing of memories is done using an optimized memory built-in-self-test (MBIST) approach, including the generation of compact models for memory. Cost functions are constructed from estimated parameters affecting MBIST, and a user is able to assign relative weights to the parameters. Estimated parameters include MBIST area, wiring congestion, and timing overhead, as well as power consumption and timing. The cost functions are minimized using optimization techniques, resulting in an optimized grouping of memory devices and an optimized schedule for MBIST testing. The estimated parameters may be derived from a compact model constructed from data experimentally-derived from various memory devices. This approach allows a circuit designer to generate and revise groupings and schedules prior to running a full design flow, saving time and cost, while still achieving high-quality results.

Abstract: Testing of memories is done using an optimized memory built-in-self-test (MBIST) approach, including the generation of compact models for memory. Cost functions are constructed from estimated parameters affecting MBIST, and a user is able to assign relative weights to the parameters. Estimated parameters include MBIST area, wiring congestion, and timing overhead, as well as power consumption and timing. The cost functions are minimized using optimization techniques, resulting in an optimized grouping of memory devices and an optimized schedule for MBIST testing. The estimated parameters may be derived from a compact model constructed from data experimentally-derived from various memory devices. This approach allows a circuit designer to generate and revise groupings and schedules prior to running a full design flow, saving time and cost, while still achieving high-quality results.