Patents by Inventor Navneet Kumar SINGH

Navneet Kumar SINGH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240334715
    Abstract: Technologies for memory on package with reduced package thickness are disclosed. In the illustrative embodiment, a die assembly includes a substrate with a processor die mounted on the top surface and a memory die mounted on the bottom surface. The die assembly is mounted on another substrate, such as a mainboard. A cavity is defined in the mainboard, and the memory die mounted on the bottom surface of the die assembly is positioned in the cavity. Positioning the memory die on the bottom surface of the die assembly can reduce the overall thickness of the die assembly and, therefore, can reduce the overall thickness of a device that incorporates the die assembly.
    Type: Application
    Filed: March 27, 2023
    Publication date: October 3, 2024
    Applicant: Intel Corporation
    Inventors: Navneet Kumar Singh, Phani Alaparthi, Samarth Alva, Ritu Bawa, Gaurav Hada, Aiswarya M. Pious
  • Publication number: 20240006873
    Abstract: Systems, apparatuses and methods may provide for power adapter technology that includes an adapter plug having a housing, a plurality of contacts positioned within the housing, wherein the plurality of contacts includes one or more configuration channel contacts, and a piezoelectric membrane positioned on an external surface of the housing, wherein the piezoelectric membrane is electrically connected to the one or more configuration channel contacts. Additionally, sink device technology may detect a signal from the piezoelectric membrane of the adapter plug via the configuration channel contact(s), wherein the signal indicates user contact with the adapter plug, and disconnect a bulk capacitor from a receptacle adjacent to the adapter plug in response to a disconnect condition associated with the user contact.
    Type: Application
    Filed: June 29, 2022
    Publication date: January 4, 2024
    Inventors: Navneet Kumar Singh, Shailendra Singh Chauhan, Aiswarya Pious, Amarjeet Kumar, Samarth Alva
  • Publication number: 20230299516
    Abstract: A back-to-back ultra-slim module (USM) includes an inline USM (USMi) connector and a top mount USM (USMt) connector. The back-to-back USM assembly can be made as a double-sided module to allow a stacked module configuration to save system area. The stacked module has a USMi module inline with the system board on one side of the system board, and a USMt module vertically offset from the other side of the system board. The stacked module can have a thermal layer between the USMi module and the USMt module.
    Type: Application
    Filed: May 25, 2023
    Publication date: September 21, 2023
    Applicant: Intel Corporation
    Inventors: Amarjeet KUMAR, Navneet Kumar SINGH, I, Samarth ALVA, Richard S. PERRY, Christopher WEST
  • Patent number: 11538731
    Abstract: Embodiments disclosed herein include electronic packages with improved thermal performance. In an embodiment, the electronic package comprises a first package substrate, a first die stack over the first package substrate, and a heat spreader over the first die stack. In an embodiment, the heat spreader comprises arms that extend out past sidewalls of the first package substrate. In an embodiment, the electronic package further comprises an interposer over and around the heat spreader, where the interposer is electrically coupled to the first package substrate by a plurality of interconnects. In an embodiment, the electronic package further comprises a second package substrate over the interposer, and a second die over the second package substrate.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: December 27, 2022
    Assignee: Intel Corporation
    Inventors: Bijendra Singh, Vikas Rao, Sandesh Geejagaaru Krishnamurthy, Navneet Kumar Singh, Unnikrishnan Gopinanthan Pillai
  • Publication number: 20220335910
    Abstract: Apparatus, systems, and methods for display panel power savings during stylus usage are disclosed. An example apparatus includes interface circuitry to receive touch event location data indicative of touch events by a user on a display screen of an electronic device; and processor circuitry to perform operations to instantiate display mapping circuitry to identify an area of the display screen covered by a portion of a body of the user based on a shape of the portion; and pixel identification circuitry to identify respective ones of pixels of the display screen in the area of the display screen; and cause a property of the respective ones of the pixels to be adjusted.
    Type: Application
    Filed: July 1, 2022
    Publication date: October 20, 2022
    Inventors: Praveen Kashyap Ananta Bhat, Navneet Kumar Singh, Samarth Alva, Aiswarya Pious, Susanta Bhattacharjee, Karthika Murthy, Mallari Hanchate, Antonio Cheng
  • Publication number: 20220316692
    Abstract: Cooling systems and apparatus for electronic devices and related methods are disclosed. An example electronic device includes a housing including a cover; a keyboard carried by the housing, the keyboard including keycaps, at least a portion of the keycaps protruding relative to the cover, a first gap between a first one of the keycaps and the cover; a backlight carried by the housing, the backlight including a first opening; and a fan carried by the housing, the first opening defining an airflow path in the housing between the fan and the first gap.
    Type: Application
    Filed: June 23, 2022
    Publication date: October 6, 2022
    Inventors: Praveen Kashyap Ananta Bhat, Bijendra Singh, Navneet Kumar Singh
  • Publication number: 20220095456
    Abstract: In one embodiment, a printed circuit board includes a first circuit board portion comprising a set of first conducting layers and one or more plated through hole (PTH) vias formed through the first conducting layers and a second circuit board portion comprising a set of second conducting layers. The second circuit board portion has an area less than an area of the first circuit board portion, and the second circuit board portion is coupled to the first circuit board portion via a laminate layer such that the first and second conducting layers are parallel with one another. The printed circuit board further includes one or more PTH vias formed through the first and second conducting layers in an area of the printed circuit board where the first and second circuit board portions overlap.
    Type: Application
    Filed: December 6, 2021
    Publication date: March 24, 2022
    Applicant: Intel Corporation
    Inventors: Arumanayagam Rajasekar, Tin Poay Chuah, Sushil Padmanabhan, Aiswarya M. Pious, Navneet Kumar Singh
  • Publication number: 20220077609
    Abstract: A connector to connect an electronic module to an edge of a first electronic circuit board is described. The module has a second electronic circuit board. The connector has a top part that houses a first row of I/Os. The top part is to be placed on a surface of the first electronic circuit board. The connector has a bottom part that houses a second row of I/Os. The bottom part is to be placed on an opposite surface of the first electronic circuit board, wherein, the top and bottom parts form inner and outer stand-offs when mater together. The inner stand-off is to reside within a through hole of the first electronic circuit board. The outer stand-off is to reside within free space off the edge of the first electronic circuit board. The second electronic circuit board is to be pressed in between the first row of I/Os and the second row of I/Os when the module is connected to the connector.
    Type: Application
    Filed: September 20, 2021
    Publication date: March 10, 2022
    Inventors: Navneet Kumar SINGH, Aiswarya M. PIOUS, Richard S. PERRY, Amarjeet KUMAR, Siva Prasad JANGILI GANGA, Gaurav HADA, Sushil PADMANABHAN, Konika GANGULY
  • Publication number: 20210350952
    Abstract: An air mover external to a mobile computing device provides enhanced cooling to the device by generating forced air delivered to the device via cooling channels connected to openings in the device chassis. If the mobile computing device is passively cooled (is a fanless device), the enhanced cooling can enable the device or device components to operate at a higher power consumption level without exceeding device/component thermal limits or for features that consume high amounts of power (e.g., fast charging) to be incorporated into the device. The air mover can be integrated into or attached to a cable that provides power to the mobile computing device. The air mover can be powered by the cable. The air mover can dynamically adjust the flow rate of the forced air based on device/component performance information (temperature, power consumption, current consumption) or operational state information of the device.
    Type: Application
    Filed: July 20, 2021
    Publication date: November 11, 2021
    Inventors: Navneet Kumar Singh, Samarth Alva, Raghavendra S. Kanivihalli, Aiswarya M. Pious, Samantha Rao, Bijendra Singh
  • Publication number: 20200312736
    Abstract: Embodiments disclosed herein include electronic packages with improved thermal performance. In an embodiment, the electronic package comprises a first package substrate, a first die stack over the first package substrate, and a heat spreader over the first die stack. In an embodiment, the heat spreader comprises arms that extend out past sidewalls of the first package substrate. In an embodiment, the electronic package further comprises an interposer over and around the heat spreader, where the interposer is electrically coupled to the first package substrate by a plurality of interconnects. In an embodiment, the electronic package further comprises a second package substrate over the interposer, and a second die over the second package substrate.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 1, 2020
    Inventors: Bijendra SINGH, Vikas RAO, Sandesh Geejagaaru KRISHNAMURTHY, Navneet Kumar SINGH, Unnikrishnan Gopinanthan PILLAI
  • Patent number: D980842
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: March 14, 2023
    Assignee: Intel Corporation
    Inventors: Prakash Kurma Raju, Ajay Kumar Vaidhyanathan, Bala Subramanya, Gurpreet Singh Sandhu, Navneet Kumar Singh, Nehakausar Shaikh Ramjan Pinjari