Patents by Inventor Navneet Yadav

Navneet Yadav has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160080221
    Abstract: A method includes receiving information describing an addition of a first site comprising at least one application to an existing network wherein the information is selected from the group consisting of type of site, planned connectivity to the site and planned policies for the site and estimating an impact on the operation of the at least one application and associated network traffic using statistical analysis of monitored data collected from a second site similar to the first site.
    Type: Application
    Filed: September 16, 2015
    Publication date: March 17, 2016
    Inventors: Kumar Ramachandran, Venkataraman Anand, Navneet Yadav, Arivu Ramasamy
  • Patent number: 7940650
    Abstract: This application describes techniques for peer-agnostic socket replication to implement graceful failover. An exemplary method to enable non-stop routing includes receiving a packet with a first routing engine of a network device having the first routing engine and a second routing engine configured as a backup routing engine, replicating, before processing the packet at a transport layer, the packet to form a replicated packet, sending the replicated packet from the first routing engine to the second routing engine, receiving, at the first routing engine, an acknowledgement from the second routing engine acknowledging reception of the replicated packet, after receiving the acknowledgment, processing the packet at the transport layer of the first routing engine to extract application-layer data and assemble a routing message, and storing the application-layer data from the processed packet in a socket associated with a routing process of the first routing engine.
    Type: Grant
    Filed: December 4, 2008
    Date of Patent: May 10, 2011
    Assignee: Juniper Networks, Inc.
    Inventors: Saurabh Sandhir, Manoj Kumar Guglani, David S. Wang, Navneet Yadav
  • Patent number: 6631466
    Abstract: A high-speed parallel pattern searching system is disclosed. The high-speed parallel pattern searching system allows the body of a data packet to be searched for one or more patterns such as a string or a series of strings. These string patterns can be defined by the grammar of regular expressions. In the invention, one or more patterns are loaded into one or more nanocomputers that operate in parallel. A control system then feeds a packet body into the participating nanocomputers such that each participating nanocomputer tests for a match. The various tests performed by the nanocomputers may be combined to perform complex searches. These nanocomputer searches are performed in parallel. Furthermore, several different searches may be combined together using control statements. A combination of these searches engines can be supported such that data is also looked at in parallel.
    Type: Grant
    Filed: May 9, 2000
    Date of Patent: October 7, 2003
    Assignee: PMC-Sierra
    Inventors: Vikram Chopra, Ajay Desai, Raghunath Iyer, Sundar Iyer, Moti Jiandani, Ajit Shelat, Navneet Yadav
  • Patent number: 6611875
    Abstract: A control system for high-speed rule processors used in a gateway system is disclosed. The gateway system employing the current invention can process packets at wire speed by using massive parallel processors, each of the processors operating concurrently and independently. Further, the processing capacities in the gateway system employing the current invention are expandable. The number of packet inspector engines may be increased and all of the engines are connected in a cascade manner. Under the control system, all of the engines operate concurrently and independently and results from each of the engines are collected sequentially through a common data bus. As such the processing speed of packets becomes relatively independent of the complexities and numbers of rules that may be applied to the packets.
    Type: Grant
    Filed: April 30, 1999
    Date of Patent: August 26, 2003
    Assignee: PMC-Sierra, Inc.
    Inventors: Vikram Chopra, Ajay Desai, Raghunath Iyer, Sundar Iyer, Moti Jiandani, Ajit Shelat, Navneet Yadav
  • Patent number: 6510509
    Abstract: A high-speed rule processing apparatus is disclosed that may be used to implement a wide variety of rule processing tasks such as network address translation, firewall protection, quality of service, IP routing, and/or load balancing. The high-speed rule processor uses an array of compare engines that operate in parallel. Each compare engine includes memory for storing instructions and operands, an arithmetic-logic for performing comparisons, and control circuitry for interpreting the instructions and operands. The results from the array of compare engines is prioritized using a priority encoding system.
    Type: Grant
    Filed: March 29, 1999
    Date of Patent: January 21, 2003
    Assignee: PMC-Sierra US, Inc.
    Inventors: Vikram Chopra, Ajay Desai, Raghunath Iyer, Sundar Iyer, Moti Jiandani, Ajit Shelat, Navneet Yadav