Abstract: This disclosure describes systems, methods, and devices for estimating dimple etch recess depth in a gate-all-around transistor. A method may include receiving, by a device, first measurements of the gate-all-around transistor, the first measurements based on first optical data from a spacer etch stage of fabricating the gate-all-around transistor; inputting, by the at least one processor, using a feed forward network, the first measurements to a machine learning model trained to estimate dimple etch recess in the gate-all-around transistor; inputting, by the at least one processor, to the machine learning model, second optical data from a dimple etch stage of fabricating the gate-all-around transistor; and generating, by the at least one processor, using the machine learning model, based on the second optical data and the first measurements, second measurements comprising the first measurements and dimple etch recess estimates for the gate-all-around transistor.