Patents by Inventor Nayanee Gupta

Nayanee Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Selective deposition to improve selectivity and structures formed thereby
    Patent number: 7358547
    Abstract: Methods and associated apparatus of forming a microelectronic structure are described. Those methods comprise providing a substrate comprising a region of higher active area density comprising source and drain recesses and a region of lower active area density comprising source and drain recesses, wherein the region of lower active area density further comprises dummy recesses, and selectively depositing a silicon alloy layer in the source, drain and dummy recesses to enhance the selectivity and uniformity of the silicon alloy deposition.
    Type: Grant
    Filed: June 13, 2005
    Date of Patent: April 15, 2008
    Assignee: Intel Corporation
    Inventors: Anand Murthy, Nayanee Gupta, Chris Auth, Glenn A. Glass
  • Methods for selective deposition to improve selectivity
    Patent number: 7129139
    Abstract: Methods and associated apparatus of forming a microelectronic structure are described. Those methods comprise providing a substrate comprising a region of higher active area density comprising source and drain recesses and a region of lower active area density comprising source and drain recesses, wherein the region of lower active area density further comprises dummy recesses, and selectively depositing a silicon alloy layer in the source, drain and dummy recesses to enhance the selectivity and uniformity of the silicon alloy deposition.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: October 31, 2006
    Assignee: Intel Corporation
    Inventors: Anand Murthy, Nayanee Gupta, Chris Auth, Glenn A. Glass
  • Methods for selective deposition to improve selectivity
    Publication number: 20060057809
    Abstract: Methods and associated apparatus of forming a microelectronic structure are described. Those methods comprise providing a substrate comprising a region of higher active area density comprising source and drain recesses and a region of lower active area density comprising source and drain recesses, wherein the region of lower active area density further comprises dummy recesses, and selectively depositing a silicon alloy layer in the source, drain and dummy recesses to enhance the selectivity and uniformity of the silicon alloy deposition.
    Type: Application
    Filed: November 10, 2005
    Publication date: March 16, 2006
    Inventors: Anand Murthy, Nayanee Gupta, Chris Auth, Glenn Glass
  • Methods for selective deposition to improve selectivity
    Publication number: 20050230760
    Abstract: Methods and associated apparatus of forming a microelectronic structure are described. Those methods comprise providing a substrate comprising a region of higher active area density comprising source and drain recesses and a region of lower active area density comprising source and drain recesses, wherein the region of lower active area density further comprises dummy recesses, and selectively depositing a silicon alloy layer in the source, drain and dummy recesses to enhance the selectivity and uniformity of the silicon alloy deposition.
    Type: Application
    Filed: June 13, 2005
    Publication date: October 20, 2005
    Inventors: Anand Murthy, Nayanee Gupta, Chris Auth, Glenn Glass
  • Methods for selective deposition to improve selectivity
    Publication number: 20050133832
    Abstract: Methods and associated apparatus of forming a microelectronic structure are described. Those methods comprise providing a substrate comprising a region of higher active area density comprising source and drain recesses and a region of lower active area density comprising source and drain recesses, wherein the region of lower active area density further comprises dummy recesses, and selectively depositing a silicon alloy layer in the source, drain and dummy recesses to enhance the selectivity and uniformity of the silicon alloy deposition.
    Type: Application
    Filed: December 22, 2003
    Publication date: June 23, 2005
    Inventors: Anand Murthy, Nayanee Gupta, Chris Auth, Glenn Glass