Abstract: In some examples, a computing device includes a first reset domain including a test controller and a configurable test logic. The computing device includes a second reset domain including a subsystem to be measured by the configurable test logic. The first reset domain is to enter a reset mode, and after exiting the reset mode, receive configuration information that configures the configurable test logic. The test controller of the first reset domain is to maintain the second reset domain in a reset mode after the first reset domain has exited the reset mode of the first reset domain, and responsive to the received configuration information for configuring the configurable test logic, provide a reset release indication to the second reset domain to allow the second reset domain to exit the reset mode of the second reset domain.

Abstract: In some examples, a computing device includes a first reset domain including a test controller and a configurable test logic. The computing device includes a second reset domain including a subsystem to be measured by the configurable test logic. The first reset domain is to enter a reset mode, and after exiting the reset mode, receive configuration information that configures the configurable test logic. The test controller of the first reset domain is to maintain the second reset domain in a reset mode after the first reset domain has exited the reset mode of the first reset domain, and responsive to the received configuration information for configuring the configurable test logic, provide a reset release indication to the second reset domain to allow the second reset domain to exit the reset mode of the second reset domain.

Abstract: An apparatus includes a host and a baseboard management controller. The baseboard management controller includes a semiconductor package; and the semiconductor package includes a memory, a security hardware processor; and a main hardware processor. The main hardware processor causes the baseboard management controller to serve as an agent that, independently from the host, responds to communications with a remote management entity to manage the host. The security hardware processor manages the storage of a secret of the host in the memory.

Abstract: A processor executes firmware to write control data describing transfer descriptors for a bus protocol engine to an address that is associated with a transfer descriptor buffer for the bus protocol engine. The bus protocol engine performs an operation according to the transfer descriptors with a slave device; the processor is part of a first semiconductor package; the bus protocol engine is part of a second semiconductor package other than the first semiconductor package; and the address corresponds to a memory of the second semiconductor package. A first physical interface of the first semiconductor package communicates with a second physical interface of the second semiconductor package to direct the control data to the memory.

Abstract: A processor executes firmware to write control data describing transfer descriptors for a bus protocol engine to an address that is associated with a transfer descriptor buffer for the bus protocol engine. The bus protocol engine performs an operation according to the transfer descriptors with a slave device; the processor is part of a first semiconductor package; the bus protocol engine is part of a second semiconductor package other than the first semiconductor package; and the address corresponds to a memory of the second semiconductor package. A first physical interface of the first semiconductor package communicates with a second physical interface of the second semiconductor package to direct the control data to the memory.

Abstract: A system includes a first physical chassis comprising a first chassis management unit (“CMU”). The first CMU is configured to communicate with a second CMU in an additional physical chassis. The first CMU is also configured to communicate for the first physical chassis and the additional physical chassis as one logical chassis.

Abstract: A system includes a first physical chassis comprising a first chassis management unit (“CMU”). The first CMU is configured to communicate with a second CMU in an additional physical chassis. The first CMU is also configured to communicate for the first physical chassis and the additional physical chassis as one logical chassis.

Abstract: In one embodiment, the invention recites a fan motor assembly with integrated redundant availability. The fan motor assembly comprises a fan motor subassembly with a plurality of replaceable fan motors, and a fan motor selector mechanism coupled to the fan motor subassembly, so that the fan motor selector mechanism selectively engages one of the plurality of replaceable fan motors to a fan. The fan motor assembly further comprises a control unit which is coupled to the fan motor selector mechanism which is configured to control the fan motor selector mechanism such that a first replaceable fan motor mechanically powers the fan while a second replaceable fan motor can be dynamically removed from the fan motor subassembly.

Abstract: A fan motor assembly with integrated redundant availability is recited. The fan motor assembly can include a fan motor subassembly with a first fan motor and a second fan motor, and a fan motor selector mechanism coupled to the fan motor subassembly, so that the fan motor selector mechanism selectively couples the first fan motor or second fan motor to a fan. The fan motor assembly can also include a control unit coupled to the fan motor selector mechanism, wherein the control unit is configured to control the fan motor selector mechanism such that either of the first fan motor and second fan motor is selectively engaged to the fan.