Abstract: In some examples, an apparatus includes a management controller for use in a computer system having a processing resource for executing an operating system (OS) of the computer system, the management controller being separate from the processing resource and to perform, based on operation of the management controller within a cryptographic boundary, management of components of the computer system, the management of components comprising power control of the computer system. The management controller is to receive sensor data, perform facial recognition based on the sensor data, and determine whether to initiate a security action responsive to the facial recognition.

Abstract: A data processing system comprises a management processor, a programmable logic device (PLD) coupled to the management processor, and a machine-readable medium (MRM). The MRM comprises a PLD configuration image to configure the PLD with image-defined logic that comprises self-verification logic and an image-defined management interface to enable the management processor to communicate with the self-verification logic. The MRM also comprises a cryptographic signature based on the PLD configuration image.

Abstract: An apparatus includes a subsystem, a first processor, a memory, a circuit and a second processor. The first processor is to execute bootstrap instructions, and the memory is to store second instructions. The circuit is to hold the first processor in reset in response to the apparatus being powered on; and the second processor is to, while the first processor is held in reset, execute the second instructions to initialize the subsystem.

Abstract: A data processing system comprises a management processor, a programmable logic device (PLD) coupled to the management processor, and a machine-readable medium (MRM). The MRM comprises a PLD configuration image to configure the PLD with image-defined logic that comprises self-verification logic and an image-defined management interface to enable the management processor to communicate with the self-verification logic. The MRM also comprises a cryptographic signature based on the PLD configuration image.

Abstract: An apparatus includes a plurality of subsystems, including a first subsystem and a second subsystem. The apparatus includes a master processor to, in response to a power on of the apparatus, execute first instructions to configure the first subsystem and provide second instructions. The apparatus further includes a slave processor to, prior to the boot of the apparatus, receive the second instructions from the master processor and execute the second instructions to configure the second subsystem.

Abstract: An apparatus includes a plurality of subsystems, including a first subsystem and a second subsystem. The apparatus includes a master processor to, in response to a power on of the apparatus, execute first instructions to configure the first subsystem and provide second instructions. The apparatus further includes a slave processor to, prior to the boot of the apparatus, receive the second instructions from the master processor and execute the second instructions to configure the second subsystem.

Abstract: An apparatus includes a subsystem, a first processor, a memory, a circuit and a second processor. The first processor is to execute bootstrap instructions, and the memory is to store second instructions. The circuit is to hold the first processor in reset in response to the apparatus being powered on; and the second processor is to, while the first processor is held in reset, execute the second instructions to initialize the subsystem.

Abstract: In some examples, an apparatus includes a management controller for use in a computer system having a processing resource for executing an operating system (OS) of the computer system, the management controller being separate from the processing resource and to perform, based on operation of the management controller within a cryptographic boundary, management of components of the computer system, the management of components comprising power control of the computer system. The management controller is to receive sensor data, perform facial recognition based on the sensor data, and determine whether to initiate a security action responsive to the facial recognition.

Abstract: An assembly includes a first central-processor-unit (CPU) printed-circuit board (PCB). The PCB is configured to accept a first processor set of processors mounted thereon. In addition, a first twin-mate arrangement of connectors is mounted on said first CPU PCB.

Abstract: A fan controller in one exemplary embodiment facilitates control over a cooling system having fans in a computing apparatus, and permits operating system and application program based software inputs as well as hardware inputs to be utilized in the control of the fans.

Abstract: A fan controller in one exemplary embodiment facilitates control over a cooling system having fans in a computing apparatus, and permits operating system and application program based software inputs as well as hardware inputs to be utilized in the control of the fans.

Abstract: In one embodiment, the invention recites a fan motor assembly with integrated redundant availability. The fan motor assembly comprises a fan motor subassembly with a first fan motor and a second fan motor, and a fan motor selector mechanism coupled to the fan motor subassembly, so that the fan motor selector mechanism selectively couples the first fan motor or second fan motor to a fan. The fan motor assembly further comprises a control unit coupled to the fan motor selector mechanism, wherein the control unit is configured to control the fan motor selector mechanism such that either of the first fan motor and second fan motor is selectively engaged to said fan.

Abstract: In one embodiment, the invention recites a fan motor assembly with integrated redundant availability. The fan motor assembly comprises a fan motor subassembly with a plurality of replaceable fan motors, and a fan motor selector mechanism coupled to the fan motor subassembly, so that the fan motor selector mechanism selectively engages one of the plurality of replaceable fan motors to a fan. The fan motor assembly further comprises a control unit which is coupled to the fan motor selector mechanism which is configured to control the fan motor selector mechanism such that a first replaceable fan motor mechanically powers the fan while a second replaceable fan motor can be dynamically removed from the fan motor subassembly.

Abstract: The present invention provides systems and methods for performing frequency margin testing of a computer system, such as a server. A system of the invention can include a controller, e.g., a BMC, internal to the computer system and a digital frequency synthesizer that can communicate with the controller and can apply clock frequency to marginable components of the computer system. In response to commands from the controller, the synthesizer generates one or more test frequencies that are applied to one or more of the marginable components. The response of the system to each of the test frequencies is then monitored.

Abstract: A control circuit that provides a control signal to control, e.g., the hardware system of a server is disclosed. The control circuit operates based on the condition of the Baseboard Manageability Controller (BMC). Asserting the control signal turns on the hardware system, and the control circuit asserts the control signal when the control circuit has not received a heartbeat pulse from the BMC for more than a predetermined time. Further, the BMC is programmed to revoke generation of its heartbeat signal once it has completed initialization, and the BMC is programmed to deterministically generate a heartbeat within a predetermined time-period triggered on connection of AC power to the system.