Abstract: A semiconductor memory device includes first conductive layers arranged in a first direction, a second conductive layer disposed at a position overlapping with the first conductive layers viewed from the first direction, a third conductive layer disposed at a position overlapping with the first conductive layers viewed from the first direction and arranged with the second conductive layer in a second direction intersecting with the first direction, a first semiconductor column opposed to the first conductive layers and the second conductive layer, a second semiconductor column opposed to the first conductive layers and the third conductive layer, and a fourth conductive layer disposed between the second conductive layer and the third conductive layer. The fourth conductive layer has a length in the second direction smaller than a length of the second conductive layer in the second direction and a length of the third conductive layer in the second direction.

Abstract: A semiconductor memory device includes first conductive layers arranged in a first direction, a second conductive layer disposed at a position overlapping with the first conductive layers viewed from the first direction, a third conductive layer disposed at a position overlapping with the first conductive layers viewed from the first direction and arranged with the second conductive layer in a second direction intersecting with the first direction, a first semiconductor column opposed to the first conductive layers and the second conductive layer, a second semiconductor column opposed to the first conductive layers and the third conductive layer, and a fourth conductive layer disposed between the second conductive layer and the third conductive layer. The fourth conductive layer has a length in the second direction smaller than a length of the second conductive layer in the second direction and a length of the third conductive layer in the second direction.

Abstract: A semiconductor memory device includes first conductive layers, second conductive layers, a semiconductor layer disposed between the first conductive layers and the second conductive layers, and a charge storage layer including a first part disposed between the first conductive layers and the semiconductor layer and a second part disposed between the second conductive layers and the semiconductor layer. This semiconductor memory device is configured to execute a first write operation in which a first program voltage is supplied to a third conductive layer which is one of the first conductive layers and a write pass voltage is supplied to a fourth conductive layer which is another of the first conductive layers, and a second write operation in which a second program voltage is supplied to the third conductive layer and to the fourth conductive layer.

Abstract: A semiconductor memory device includes first conductive layers, second conductive layers, a semiconductor layer disposed between the first conductive layers and the second conductive layers, and a charge storage layer including a first part disposed between the first conductive layers and the semiconductor layer and a second part disposed between the second conductive layers and the semiconductor layer. This semiconductor memory device is configured to execute a first write operation in which a first program voltage is supplied to a third conductive layer which is one of the first conductive layers and a write pass voltage is supplied to a fourth conductive layer which is another of the first conductive layers, and a second write operation in which a second program voltage is supplied to the third conductive layer and to the fourth conductive layer.

Abstract: A semiconductor memory device includes a plurality of conductive layers, a semiconductor layer opposed to the plurality of conductive layers, and an electric charge accumulation portion disposed between the semiconductor layer and the plurality of conductive layers. The electric charge accumulation portion includes a plurality of first electric charge accumulation portions opposed to the plurality of conductive layers, and a plurality of second electric charge accumulation portions disposed in positions different from the plurality of first electric charge accumulation portions. A distance between the first electric charge accumulation portion and the semiconductor layer is smaller than a distance between the second electric charge accumulation portion and the semiconductor layer. A distance between the second electric charge accumulation portion and the conductive layers is smaller than a distance between the first electric charge accumulation portion and the conductive layers.

Abstract: According to one embodiment, first and second conductive layers are stacked in a first direction. The second conductive layers are spaced from the first conductive layers. Insulation regions are provided between the first and second conductive layers. A pillar is arranged between the first and second conductive layers and between the insulation regions. The pillar includes a charge storage film, a first insulation film, and a semiconductor layer, which are provided sequentially from the first conductive layers. A second insulation film is provided between the charge storage film and the first conductive layers. A portion of the charge storage film is provided between one of the insulation regions and the first conductive layers at an end of a portion where the first conductive layers and the pillar face each other.

Abstract: A semiconductor memory device according to an embodiment includes a substrate, first and second conductive layers, and a first pillar. The first conductive layer is provided above the substrate and includes a first N-type semiconductor region and a first P-type semiconductor region. The second conductive layers are provided above the first conductive layer and stacked at intervals. The first pillar includes a first semiconductor layer and a first insulating layer. The first semiconductor layer is provided through the second conductive layers and is in contact with each of the first N-type semiconductor region and the first P-type semiconductor region. The first insulating layer is provided between the first semiconductor layer and the second conductive layers.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a plurality of electrode films arranged along a first direction with an air gap interposed, the first direction crossing a surface of the substrate, a semiconductor member extending in the first direction, a charge storage member provided between the semiconductor member and each of the electrode films, and a high dielectric constant film provided along an outer surface of the air gap, a relative dielectric constant of the high dielectric constant film being higher than a relative dielectric constant of silicon oxide.

Abstract: According to one embodiment, first and second conductive layers are stacked in a first direction. The second conductive layers are spaced from the first conductive layers. Insulation regions are provided between the first and second conductive layers. A pillar is arranged between the first and second conductive layers and between the insulation regions. The pillar includes a charge storage film, a first insulation film, and a semiconductor layer, which are provided sequentially from the first conductive layers. A second insulation film is provided between the charge storage film and the first conductive layers. A portion of the charge storage film is provided between one of the insulation regions and the first conductive layers at an end of a portion where the first conductive layers and the pillar face each other.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a plurality of electrode films arranged along a first direction with an air gap interposed, the first direction crossing a surface of the substrate, a semiconductor member extending in the first direction, a charge storage member provided between the semiconductor member and each of the electrode films, and a high dielectric constant film provided along an outer surface of the air gap, a relative dielectric constant of the high dielectric constant film being higher than a relative dielectric constant of silicon oxide.

Abstract: On a silicon substrate 120 of a semiconductor device, a field oxide film 101 is provided. On the field oxide film 101, two fuses 104 are provided. Directly below the fuses 104 in the silicon substrate 120, an n-type well 102 is provided. Besides the n-type well 102, a p-type well 103 is provided in such a manner as to surround a region directly under the fuses 104 in the silicon substrate 120. A cover insulating film 108 is provided over the silicon substrate 120 and the field oxide film 101. A seal ring composed of a contact 106 and an interconnection 107 is embedded in the cover insulating film 108 so as to surround the fuses 104.

Abstract: On a silicon substrate 120 of a semiconductor device, a field oxide film 101 is provided. On the field oxide film 101, two fuses 104 are provided. Directly below the fuses 104 in the silicon substrate 120, an n-type well 102 is provided. Besides the n-type well 102, a p-type well 103 is provided in such a manner as to surround a region directly under the fuses 104 in the silicon substrate 120. A cover insulating film 108 is provided over the silicon substrate 120 and the field oxide film 101. A seal ring composed of a contact 106 and an interconnection 107 is embedded in the cover insulating film 108 so as to surround the fuses 104.