Patents by Inventor Nazanin Darbanian

Nazanin Darbanian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9891646
    Abstract: Operational mode changes in a system-on-a-chip (SoC) integrated circuit in a complex device such as a mobile phone cause spikes in current demand which can cause voltage droops that disrupt operation of the SoC. A hybrid parallel power supply capacitively couples a switching-mode power supply and a low-dropout voltage regulator in parallel to provide high efficiency and fast response times. The low-dropout voltage regulator may include a class-AB operational transconductance amplifier driving the coupling capacitor. The switching-mode power supply and the low-dropout voltage regulator can regulate their outputs to slightly difference voltage levels. This can allow the switching-mode power supply to supply most of the SoC's current demands.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: February 13, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Zhengming Fu, James Thomas Doyle, Nazanin Darbanian, Shree Krishna Pandey, Yi Cao
  • Patent number: 9785222
    Abstract: Operational mode changes in a system-on-a-chip (SoC) integrated circuit in a complex device such as a mobile phone cause spikes in current demand which can cause voltage droops that disrupt operation of the SoC. A hybrid parallel power supply connects a switching-mode power supply and a low-dropout voltage regulator in parallel to provide high efficiency and fast response times. Integration of the voltage regulator on the SoC reduces parasitic impedance be between the voltage regulator and the load to aid in reducing voltage droops. The switching-mode power supply and the low-dropout voltage regulator can regulate their outputs to slightly difference voltage levels. This can allow the switching-mode power supply to supply most of the SoC's current demands.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: October 10, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: James Thomas Doyle, Zhengming Fu, Farsheed Mahmoudi, Amirali Shayan Arani, Nazanin Darbanian
  • Publication number: 20160216723
    Abstract: Operational mode changes in a system-on-a-chip (SoC) integrated circuit in a complex device such as a mobile phone cause spikes in current demand which can cause voltage droops that disrupt operation of the SoC. A hybrid parallel power supply capacitively couples a switching-mode power supply and a low-dropout voltage regulator in parallel to provide high efficiency and fast response times. The low-dropout voltage regulator may include a class-AB operational transconductance amplifier driving the coupling capacitor. The switching-mode power supply and the low-dropout voltage regulator can regulate their outputs to slightly difference voltage levels. This can allow the switching-mode power supply to supply most of the SoC's current demands.
    Type: Application
    Filed: January 27, 2015
    Publication date: July 28, 2016
    Inventors: Zhengming Fu, James Thomas Doyle, Nazanin Darbanian, Shree Krishna Pandey, Yi Cao
  • Publication number: 20160179181
    Abstract: Operational mode changes in a system-on-a-chip (SoC) integrated circuit in a complex device such as a mobile phone cause spikes in current demand which can cause voltage droops that disrupt operation of the SoC. A hybrid parallel power supply connects a switching-mode power supply and a low-dropout voltage regulator in parallel to provide high efficiency and fast response times. Integration of the voltage regulator on the SoC reduces parasitic impedance be between the voltage regulator and the load to aid in reducing voltage droops. The switching-mode power supply and the low-dropout voltage regulator can regulate their outputs to slightly difference voltage levels. This can allow the switching-mode power supply to supply most of the SoC's current demands.
    Type: Application
    Filed: December 22, 2014
    Publication date: June 23, 2016
    Inventors: James Thomas Doyle, Zhengming Fu, Farsheed Mahmoudi, Amirali Shayan Arani, Nazanin Darbanian
  • Publication number: 20150310990
    Abstract: Aspects of a method of manufacturing a capacitor are provided. The method includes layering a plurality of dielectric plates. The plurality of dielectric plates includes a first dielectric plate having a first conductive region and a second conductive region on a surface of the first dielectric plate. The method further includes forming an inner electrode through an axis of the layered plurality of dielectric plates. The inner electrode electrically couples to the first conductive region on the surface of the first dielectric plate. The method further includes forming an outer electrode, where the outer electrode electrically couples to the second conductive region on the surface of the first dielectric plate.
    Type: Application
    Filed: April 24, 2014
    Publication date: October 29, 2015
    Applicant: QUALCOMM INCORPORATED
    Inventors: Lalan Jee Mishra, Shree Krishna Pandey, Nazanin Darbanian, John David Eaton
  • Publication number: 20150255216
    Abstract: A capacitor with low equivalent series inductance includes multiple electrode layers arranged in parallel with alternating ones of the electrode layers connected together to form the two electrodes of the capacitor. A first set of the electrode layers are connected by an outer wall. A second set of the electrode layers are connected by a central post. Terminals on the capacitor can be spaced on a surface so that signals can be conveniently routed when the capacitor is mounted on or in a printed circuit board or integrated circuit package. Terminals can be included on opposing surfaces of the capacitors to provide for stacking. Additionally, one of the terminals substantially surrounds the other terminal and can provide electromagnetic shielding.
    Type: Application
    Filed: March 7, 2014
    Publication date: September 10, 2015
    Applicant: QUALCOMM INCORPORATED
    Inventors: Lalan Jee Mishra, Shree Krishna Pandey, Irfan Khan, Nazanin Darbanian, John David Eaton
  • Patent number: 8488370
    Abstract: Embodiments and examples of differential threshold voltage non-volatile memories and related methods are described herein. Other embodiments, examples thereof, and related methods are also disclosed herein.
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: July 16, 2013
    Assignee: Arizona Board of Regents, a body corporate of the State of Arizona, Acting for and on behalf of Arizona State University
    Inventors: Sameer M. Venugopal, David R. Allee, Lawrence T Clark, Nazanin Darbanian
  • Publication number: 20110261634
    Abstract: Embodiments and examples of differential threshold voltage non-volatile memories and related methods are described herein. Other embodiments, examples thereof, and related methods are also disclosed herein.
    Type: Application
    Filed: April 8, 2011
    Publication date: October 27, 2011
    Applicant: Arizona Board of Regents, for and on behalf of Arizona State University
    Inventors: Sameer M. Venugopal, David R. Allee, Lawrence T. Clark, Nazanin Darbanian
  • Publication number: 20070033000
    Abstract: A non-iterative frequency domain method for the accurate and efficient simulation of nonlinear systems is presented. In one aspect of the present invention, simulating a nonlinear system is accomplished by first modeling the system and generating parameters that describe the nonlinear system. The system is represented in the frequency domain as an inverse convolution equation (ICE), comprising cascaded convolutions and frequency representations of known and unknown signals. Next, the order of the ICE is determined based upon the degree of nonlinearity in the system. Finally, a general ICE solver algorithm is adapted to the ICE order of the frequency model, and the specific ICE solver algorithm is applied to in order to solve for an unknown signal. In another aspect of the invention, the non-iterative method for simulating nonlinear systems is combined with cross-referenced coordinate (CRC) techniques in order to increase the computational efficiency of the simulation.
    Type: Application
    Filed: July 19, 2006
    Publication date: February 8, 2007
    Inventors: Shahin Farahani, Sayfe Kiaei, Nazanin Darbanian
  • Publication number: 20060052988
    Abstract: A method and system of simulating components using a compressed signal representation. In some embodiments compressed vector based equivalent signals and blocks are used to model signal processing systems, in particular RF wireless components.
    Type: Application
    Filed: November 21, 2003
    Publication date: March 9, 2006
    Inventors: Shahin Farahani, Sayfe Kiaei, Nazanin Darbanian