Abstract: Techniques and mechanisms for sensing a voltage difference across two interconnect structures of a multi-chip packaged device. In an embodiment, the interconnect structures provide respective voltages to each of multiple integrated circuit (IC) chips of the packaged device. Switch circuitry of the packaged device is operable to provide any of multiple modes which each switchedly couple a voltage sensor to a different respective one of various sample point pairs of the interconnect structures. Control circuitry operates the switch circuitry to selectively provide one of the multiple modes based on an indication of a workload to be performed with one or more of the IC chips. In another embodiment, the voltage sensor senses the voltages each at a respective sample point of a sample point pair which corresponds to the selected mode of the switch circuitry.

Abstract: Some embodiments include apparatuses having an input node; an electrostatic discharge protection circuitry including a first diode including a cathode coupled to the input node, and an anode coupled to a ground node; a second diode including an anode coupled to the input node, and a cathode coupled to a circuit node; a clamp circuit coupled to the circuit node; and a current limiting circuit coupled between the circuit node and a supply node.

Abstract: A scheme is provided for a processor to measure or estimate the dynamic capacitance (Cdyn) associated with an executing application and take a proportional throttling action. Proportional throttling has significantly less impact on performance and hence presents an opportunity to get back the lost bins and proportionally clip power if it exceeds a specification threshold. The ability to infer a magnitude of power excursion of a power virus event (and hence, the real Cdyn) above a set power threshold limit enables the processor to proportionally adjust the processor operating frequency to bring it back under the limit. With this scheme, the processor distinguishes a small power excursion versus a large one and reacts proportionally, yielding better performance.

Abstract: An adaptive or dynamic power virus control scheme (hardware and/or software) that dynamically adjusts maximum dynamic capacitance (CdynMax) and corresponding maximum frequency (POnMax) setting per application executed on a processor core. A power management unit monitors telemetry such as a number of throttled cycles due to CdynMax threshold excursions cycles for the processor core and a cost of average cycle Cdyn cost for the processor core. As the number of throttling cycles increases for the processor core, the aCode firmware of the power management unit decides to increase the Cdyn level or threshold for that core (e.g., to make the threshold less aggressive). As the average Cdyn cost over a number of cycles becomes lower than a threshold, aCode adjusts the threshold to a lower threshold (e.g., more aggressive threshold) and lower Cdyn.

Abstract: The present disclosure describes a circuit for managing power and heat. The circuit includes a motherboard voltage regulator to supply a current to a loadline. The circuit includes a sense point coupled to the loadline, the circuit to measure a sensed voltage at the sense point. The circuit also includes a comparator to compare the sensed voltage to a reference voltage. An output of the comparator is used to indicate a level of current being provided by the motherboard voltage regulator.

Abstract: A circuit that enables a safe power-on sequencing is described. The circuit enables a processor to be powered by an internal or external voltage source. The circuit detects for the presence of an external voltage regulator. If an external voltage generator is not providing a valid voltage source to the processor, the circuit enables an internal voltage regulator to provide a stable voltage source.

Abstract: A voltage reference generator for a hysteresis circuit, comprising a first originator circuit to generate a first reference voltage; a second originator circuit to generate a second reference voltage; and a selector circuit, coupled to the first and second originator circuits, to select one of the first and second reference voltages to be an output reference voltage based upon an input signal to the hysteresis circuit undertaking a low-to-high or a high-to-low signal transition respectively. The first originator circuit includes a first plurality of channel devices selected from either p-channel devices or n-channel devices and the second originator circuit includes a second plurality of channel devices selected from the other one of the p-channel devices and the n-channel devices.