Abstract: A new method and apparatus are used to check for segment limit violations during memory access. When a segment descriptor is retrieved during the initialization of a segment, the segment limit from the segment descriptor is used to create five limits. The five limits are the last possible address within the segment for each size of memory access. During a subsequent memory access, the limit corresponding to the segment being accessed and the length of memory access is selected. The selected limit is compared against the address of the memory access to determine if a limit violation has occurred. If a limit violation has occurred, a flag is set that, when read, will cause an exception.

Abstract: A system and method are described for maintaining synchronization of information propagating through multiple front-end pipelines operating in parallel. In general, these multiple front-end pipelines become asynchronous in response to a stall condition and re-establish synchronization by flushing both front-end pipelines as well as by selectively releasing these front-end pipelines from their stall condition at different periods of time.

Abstract: A method and device for identifying boundaries between variable length instructions in a packet of instruction bytes includes examining each instruction byte in a first portion of the packet, marking each instruction byte in the first portion as one of an end byte and a non-end byte in response to the examining act, and marking each instruction byte in a second portion of the packet as a predetermined one of an end byte and a non-end byte.

Abstract: In a microprocessor, an Instruction scheduler 30 includes a dependency matrix 36 and a waiting buffer 34. A dependency determination unit 32 receives instructions to be executed, forwards the instructions to the waiting buffer 34, determines if any dependency exists between the instructions, and forwards the dependency information to the dependency matrix 36 in the form of a dependency vector 40. Dependency matrix 36 periodically determines whether any of the instructions contained in the waiting buffer 34 are ready to be executed, that is, no dependencies exist for that instruction. All identified instructions are then assigned to a current wave to be dispatched. The identified instructions are then dispatched for execution as execution resources become available. As each instruction is dispatched for execution in the waiting buffer 34, the dependency vector 40 for all dependent instructions is cleared for subsequent execution.

Abstract: A method for guaranteeing minimum variable scheduling distance between instructions in a processor includes receiving a plurality of instructions and determining the post-ready latency of each instruction. Each instruction is then scheduled for execution so that the instruction follows an earlier instruction by an amount of time at least equal to the post-ready latency of the instruction.

Abstract: A queue structure includes a plurality of entries, a plurality of ports coupled to the entries, a plurality of enable lines coupled to the entries and the ports, and control logic. Each enable line is adapted to enable a selected port to communicate with a selected entry. The control logic is adapted to enable at least two enable lines and allow at least one of the ports to communicate with at least two of the entries concurrently. A method for storing data in a queue is provided. The queue includes a plurality of entries, a plurality of ports coupled to the entries, and a plurality of enable lines coupled to the entries and the ports. Each enable line is adapted to enable a selected port to communicate with a selected entry. The method includes receiving a first instruction on one of the ports. A first enable line is enabled to allow the port to communicate with a first entry. The first instruction is stored in the first entry.

Abstract: A method for handling dynamic structural hazards and exceptions by using post-ready latency, including: receiving a plurality of instructions; selecting a first instruction whose execution can cause an exception; assigning a post-ready latency to a second instruction that follows the first instruction; and scheduling for execution the first instruction and the second instruction separated from the first instruction by an amount of time at least equal to the post-ready latency of the second instruction.

Abstract: A microprocessor includes an instruction fetch unit, a branch prediction unit, and a decode unit. The instruction fetch unit is adapted to retrieve a plurality of program instructions. The program instructions include serialization initiating instructions and branch instructions. The branch prediction unit is adapted to generate branch predictions for the branch instructions, direct the instruction fetch unit to retrieve the program instructions in an order corresponding to the branch predictions, and redirect the instruction fetch unit based on a branch misprediction. The branch prediction unit is further adapted to store a redirect address corresponding to the branch misprediction. The decode unit is adapted to decode the program instructions into microcode.

Abstract: A system for accelerating instruction restart in a microprocessor. An instruction is fetched. The instruction is placed in a macro-instruction queue and sent to the decoder. The instruction is decoded in order to produce at least one micro-operation. The micro-operation is executed, and the microprocessor checks for instruction restart conditions. If an instruction restart condition is found, the instruction restart function is performed. The instruction restart function includes decoding the instruction stored in the macro-instruction queue and executing the corresponding micro-operations.

Abstract: A microarchitecture that accommodates divergent instruction sets having different data sizes and addressing modes utilizes a mechanism for translating a generic flow for an instruction into specific operations at run-time. These generic flows use a special class of micro-ops (uops), called "super-uops" (or "Suops)" which are translated into a variable number of regular (i.e., simple) uops. A first-level decoder translates macroinstructions into either simple micro-ops or one or more super-uops which represent one or more sequences of one or more simple uops. A second-level decoder is responsible for converting the super-uops into the appropriate micro-op sequence based upon a set of arguments associated with the super-uop and attributes of the macroinstruction.