Abstract: An imaging system may include an array of image pixels. The array of image pixels may be provided with one or more rows and columns of optically shielded dark image pixels. The dark image pixels may be used to produce verification image data that follows the same pixel-to-output data path of light-receiving pixels. The output signals from dark pixels may be continuously or intermittently compared with a set of expected output signals to verify that the imaging system is functioning properly. In some arrangements, verification image data may include a current frame number that is encoded into the dark pixels. The encoded current frame number may be compared with an expected current frame number. In other arrangements, dark pixels may be configured to have a predetermined pattern of conversion gain levels. The output signals may be compared with a “golden” image or other predetermined set of expected output signals.

Abstract: An imaging system may include an array of image pixels. The array of image pixels may be provided with one or more rows and columns of optically shielded dark image pixels. The dark image pixels may be used to produce verification image data that follows the same pixel-to-output data path of light-receiving pixels. The output signals from dark pixels may be continuously or intermittently compared with a set of expected output signals to verify that the imaging system is functioning properly. In some arrangements, verification image data may include a current frame number that is encoded into the dark pixels. The encoded current frame number may be compared with an expected current frame number. In other arrangements, dark pixels may be configured to have a predetermined pattern of conversion gain levels. The output signals may be compared with a “golden” image or other predetermined set of expected output signals.

Abstract: An imaging system may include an array of image pixels. The array of image pixels may be provided with one or more rows and columns of optically shielded dark image pixels. The dark image pixels may be used to produce verification image data that follows the same pixel-to-output data path of light-receiving pixels. The output signals from dark pixels may be continuously or intermittently compared with a set of expected output signals to verify that the imaging system is functioning properly. In some arrangements, verification image data may include a current frame number that is encoded into the dark pixels. The encoded current frame number may be compared with an expected current frame number. In other arrangements, dark pixels may be configured to have a predetermined pattern of conversion gain levels. The output signals may be compared with a “golden” image or other predetermined set of expected output signals.

Abstract: An Electronic device may include a master camera module, a slave camera module, and host subsystems. The master camera module may control some of the operations of the slave camera module. The master camera module may transmit data to the slave camera module. The master camera module may interrupt data transmission to the slave camera module, when a delay-sensitive event occurs, to transmit information corresponding to the delay-sensitive event. The slave camera module may respond to the event information with a predetermined fixed delay relative to the occurrence of the event at the master camera module.

Abstract: An imaging system may include an array of image pixels. The array of image pixels may be provided with one or more rows and columns of optically shielded dark image pixels. The dark image pixels may be used to produce verification image data that follows the same pixel-to-output data path of light-receiving pixels. The output signals from dark pixels may be continuously or intermittently compared with a set of expected output signals to verify that the imaging system is functioning properly. In some arrangements, verification image data may include a current frame number that is encoded into the dark pixels. The encoded current frame number may be compared with an expected current frame number. In other arrangements, dark pixels may be configured to have a predetermined pattern of conversion gain levels. The output signals may be compared with a “golden” image or other predetermined set of expected output signals.

Abstract: An Electronic device may include a master camera module, a slave camera module, and host subsystems. The master camera module may control some of the operations of the slave camera module. The master camera module may transmit data to the slave camera module. The master camera module may interrupt data transmission to the slave camera module, when a delay-sensitive event occurs, to transmit information corresponding to the delay-sensitive event. The slave camera module may respond to the event information with a predetermined fixed delay relative to the occurrence of the event at the master camera module.

Abstract: This is generally directed to systems and methods for control of two or more devices through a shared control bus. For example, the devices can be coupled to a host system through the control bus. In some embodiments, the devices can be configured by the host system through address select pins of the devices. For example, the host system can sequentially program each device to change its default address to a unique address. In some embodiments, an event can be propagated through each device, thus resulting in each device receiving the event at a different time. In some embodiments, configuration by the host system can include programming each device with a value representing its own position in the chain. In this case, a device can use this value to delay its response to the event, thereby allowing all the devices in the chain to respond to the event simultaneously.

Abstract: A variable rate image sensor outputs pixel data at a variable rate using lookup tables to selectively read out particular rows at particular times. The readout rate is not constant, allowing for a smaller image buffer in the overall system.

Abstract: This is generally directed to systems and methods for control of two or more devices through a shared control bus. For example, the devices can be coupled to a host system through the control bus. In some embodiments, the devices can be configured by the host system through address select pins of the devices. For example, the host system can sequentially program each device to change its default address to a unique address. In some embodiments, an event can be propagated through each device, thus resulting in each device receiving the event at a different time. In some embodiments, configuration by the host system can include programming each device with a value representing its own position in the chain. In this case, a device can use this value to delay its response to the event, thereby allowing all the devices in the chain to respond to the event simultaneously.

Abstract: A variable rate image sensor outputs pixel data at a variable rate using lookup tables to selectively read out particular rows at particular times. The readout rate is not constant, allowing for a smaller image buffer in the overall system.

Abstract: A memory device comprising memory cells having volatile and non-volatile memory portions. The volatile memory portion of each cell includes circuitry for performing RAM functions while the non-volatile memory portion comprises circuitry defining pre-coded data. The memory device comprises a mechanism to operate an initialization sequence, which sets the initial state of the volatile memory portion of each memory cell to the pre-coded data defined in the associated non-volatile memory portion. The initialization sequence allows the initial state of each memory cell's volatile portion to be re-established after power has been applied to the memory device.

Abstract: A memory device comprising memory cells having volatile and non-volatile memory portions. The volatile memory portion of each cell includes circuitry for performing RAM functions while the non-volatile memory portion comprises circuitry defining pre-coded data. The memory device comprises a mechanism to operate an initialization sequence, which sets the initial state of the volatile memory portion of each memory cell to the pre-coded data defined in the associated non-volatile memory portion. The initialization sequence allows the initial state of each memory cell's volatile portion to be re-established after power has been applied to the memory device.

Abstract: A computer system includes a central processor unit (“CPU”), a dynamic random access memory (“DRAM”) device, a key storage device storing a decryption key, a decryption engine and a system controller coupling the CPU to the DRAM. All of these components are fabricated on a common integrated circuit substrate so that interconnections between these components are protected from unauthorized access. The system controller is also coupled through to a non-volatile memory that stores a computer program that has been encrypted. In operation, the computer program is transferred through the system controller to the decryption engine, which uses the decryption key to decrypt the computer program. The CPU executes the encrypted program, and, in doing so, transfers data between the CPU and the system memory. This data is protected from unauthorized access because the connections between the CPU and the system memory are internal to the integrated circuit.

Abstract: A pipelined computer processor is presented that reduces data hazards such that high processor utilization is attained. The processor restructures a set of instructions to operate concurrently on multiple pieces of data in multiple passes. One subset of instructions operates on one piece of data while different subsets of instructions operate concurrently on different pieces of data. A validity pipeline tracks the priming and draining of the pipeline processor to ensure that only valid data is written to registers or memory. Pass-dependent addressing is provided to correctly address registers and memory for different pieces of data.

Abstract: A system and method for distributed cache. Cache tag storage and cache data storage are maintained in separate pipeline stages. Cache tag storage is operated by a data producer. Cache data storage is operated by a data consumer. Cache hits and misses are determined by the data producer prior to any operations being performed by the processor. In the event of a cache miss, produced data is sent to the processor to be processed. In the event of a cache hit, the cache address of the corresponding previously processed data is sent to the data consumer so that the corresponding processed data unit can be retrieved from cache data storage.

Abstract: A computer system includes a central processor unit (“CPU”), a dynamic random access memory (“DRAM”) device, a key storage device storing a decryption key, a decryption engine and a system controller coupling the CPU to the DRAM. All of these components are fabricated on a common integrated circuit substrate so that interconnections between these components are protected from unauthorized access. The system controller is also coupled through to a non-volatile memory that stores a computer program that has been encrypted. In operation, the computer program is transferred through the system controller to the decryption engine, which uses the decryption key to decrypt the computer program. The CPU executes the encrypted program, and, in doing so, transfers data between the CPU and the system memory. This data is protected from unauthorized access because the connections between the CPU and the system memory are internal to the integrated circuit.

Abstract: A system and method for distributed cache. Cache tag storage and cache data storage are maintained in separate pipeline stages. Cache tag storage is operated by a data producer. Cache data storage is operated by a data consumer. Cache hits and misses are determined by the data producer prior to any operations being performed by the processor. In the event of a cache miss, produced data is sent to the processor to be processed. In the event of a cache hit, the cache address of the corresponding previously processed data is sent to the data consumer so that the corresponding processed data unit can be retrieved from cache data storage.

Abstract: A system and method for distributed cache. Cache tag storage and cache data storage are maintained in separate pipeline stages. Cache tag storage is operated by a data producer. Cache data storage is operated by a data consumer. Cache hits and misses are determined by the data producer prior to any operations being performed by the processor. In the event of a cache miss, produced data is sent to the processor to be processed. In the event of a cache hit, the cache address of the corresponding previously processed data is sent to the data consumer so that the corresponding processed data unit can be retrieved from cache data storage.

Abstract: A system and method for distributed cache. Cache tag storage and cache data storage are maintained in separate pipeline stages. Cache tag storage is operated by a data producer. Cache data storage is operated by a data consumer. Cache hits and misses are determined by the data producer prior to any operations being performed by the processor. In the event of a cache miss, produced data is sent to the processor to be processed. In the event of a cache hit, the cache address of the corresponding previously processed data is sent to the data consumer so that the corresponding processed data unit can be retrieved from cache data storage.

Abstract: A data transfer device for coupling a processor to a system bus. The data transfer device includes data packers and unpackers for converting between data blocks of a first size and data blocks of a second size, e.g. between bytes or words and longwords. The data transfer device also includes an internal buffer memory system for storing the data being transferred. The processor and system bus are selectively coupled, each one at a time, via a direct data path, to the internal buffer memory system permitting both the processor and the system bus to independently read and write data, each at their normal data transfer rate.