Abstract: The inhibit voltage is a voltage applied to wordlines adjacent to a program wordline having a memory cell to write during the program operation. The inhibit voltage for a program operation can be ramped up during the program pulse. Instead of applying a constant high inhibit voltage that results in the initial boosted channel potential reducing drastically due to leakage, a system can start the inhibit voltage lower and ramp the inhibit voltage up during the program pulse. The ramping up can be a continuous ramp or in finite discrete steps during the program pulse. Such ramping of inhibit voltage can provide better tradeoff between program disturb and inhibit disturb.

Abstract: The inhibit voltage is a voltage applied to wordlines adjacent to a program wordline having a memory cell to write during the program operation. The inhibit voltage for a program operation can be ramped up during the program pulse. Instead of applying a constant high inhibit voltage that results in the initial boosted channel potential reducing drastically due to leakage, a system can start the inhibit voltage lower and ramp the inhibit voltage up during the program pulse. The ramping up can be a continuous ramp or in finite discrete steps during the program pulse. Such ramping of inhibit voltage can provide better tradeoff between program disturb and inhibit disturb.

Abstract: The inhibit voltage is a voltage applied to wordlines adjacent to a program wordline having a memory cell to write during the program operation. The inhibit voltage for a program operation can be ramped up during the program pulse. Instead of applying a constant high inhibit voltage that results in the initial boosted channel potential reducing drastically due to leakage, a system can start the inhibit voltage lower and ramp the inhibit voltage up during the program pulse. The ramping up can be a continuous ramp or in finite discrete steps during the program pulse. Such ramping of inhibit voltage can provide better tradeoff between program disturb and inhibit disturb.

Abstract: Methods and apparatus related to a mechanism for quickly adapting garbage collection resource allocation for an incoming I/O (Input/Output) workload are described. In one embodiment, non-volatile memory stores data corresponding to a first workload and a second workload. Allocation of one or more resources in the non-volatile memory is determined based at least in part on a determination of an average validity of one or more blocks, where the one or more candidate bands are to be processed during operation of the first workload or the second workload. Other embodiments are also disclosed and claimed.

Abstract: The inhibit voltage is a voltage applied to wordlines adjacent to a program wordline having a memory cell to write during the program operation. The inhibit voltage for a program operation can be ramped up during the program pulse. Instead of applying a constant high inhibit voltage that results in the initial boosted channel potential reducing drastically due to leakage, a system can start the inhibit voltage lower and ramp the inhibit voltage up during the program pulse. The ramping up can be a continuous ramp or in finite discrete steps during the program pulse. Such ramping of inhibit voltage can provide better tradeoff between program disturb and inhibit disturb.

Abstract: Methods and apparatus related to a mechanism for quickly adapting garbage collection resource allocation for an incoming I/O (Input/Output) workload are described. In one embodiment, non-volatile memory stores data corresponding to a first workload and a second workload. Allocation of one or more resources in the non-volatile memory is determined based at least in part on a determination of an average validity of one or more blocks, where the one or more candidate bands are to be processed during operation of the first workload or the second workload. Other embodiments are also disclosed and claimed.

Abstract: The inhibit voltage is a voltage applied to wordlines adjacent to a program wordline having a memory cell to write during the program operation. The inhibit voltage for a program operation can be ramped up during the program pulse. Instead of applying a constant high inhibit voltage that results in the initial boosted channel potential reducing drastically due to leakage, a system can start the inhibit voltage lower and ramp the inhibit voltage up during the program pulse. The ramping up can be a continuous ramp or in finite discrete steps during the program pulse. Such ramping of inhibit voltage can provide better tradeoff between program disturb and inhibit disturb.

Abstract: The inhibit voltage is a voltage applied to wordlines adjacent to a program wordline having a memory cell to write during the program operation. The inhibit voltage for a program operation can be ramped up during the program pulse. Instead of applying a constant high inhibit voltage that results in the initial boosted channel potential reducing drastically due to leakage, a system can start the inhibit voltage lower and ramp the inhibit voltage up during the program pulse. The ramping up can be a continuous ramp or in finite discrete steps during the program pulse. Such ramping of inhibit voltage can provide better tradeoff between program disturb and inhibit disturb.

Abstract: Described herein are an apparatus, system, and method for refreshing a non-volatile memory. The method comprises loading a time stamp, corresponding to data in a data location of a non-volatile memory, to a register; determining an elapsed time, corresponding to the data in the data location, according to the loaded time stamp; and refreshing data of the data location for which it is determined that the elapsed time exceeds a refresh time associated with the non-volatile memory.

Abstract: A method and apparatus for improving the endurance of flash memories. In one embodiment of the invention, a high electric field is provided to the control gate of a flash memory module. The high electric field applied to the flash memory module removes trapped charges between a control gate and an active area of the flash memory module. In one embodiment of the invention, the high electric field is applied to the control gate of the flash memory module prior to an erase operation of the flash memory module. By applying a high electric field to the control gate of the flash memory module, embodiments of the invention improve the Program/Erase cycling degradation of the single-level or multi-level cells of the flash memory module.

Abstract: Described herein are an apparatus, system, and method for refreshing a non-volatile memory. The method comprises loading a time stamp, corresponding to data in a data location of a non-volatile memory, to a register; determining an elapsed time, corresponding to the data in the data location, according to the loaded time stamp; and refreshing data of the data location for which it is determined that the elapsed time exceeds a refresh time associated with the non-volatile memory.

Abstract: A method and apparatus for improving the endurance of flash memories. In one embodiment of the invention, a high electric field is provided to the control gate of a flash memory module. The high electric field applied to the flash memory module removes trapped charges between a control gate and an active area of the flash memory module. In one embodiment of the invention, the high electric field is applied to the control gate of the flash memory module prior to an erase operation of the flash memory module. By applying a high electric field to the control gate of the flash memory module, embodiments of the invention improve the Program/Erase cycling degradation of the single-level or multi-level cells of the flash memory module.

Abstract: A method and device using bitline-bitline capacitance between adjacent bitlines to boost seed voltage in a memory device are provided. The method may include a precharge phase, a boost phase, an equalize phase, and a lock in phase. In one embodiment, the method may include boosting the seed voltage twice. The bitlines may be divided into one or more segments.

Abstract: A method and device using bitline-bitline capacitance between adjacent bitlines to boost seed voltage in a memory device are provided. The method may include a precharge phase, a boost phase, an equalize phase, and a lock in phase. In one embodiment, the method may include boosting the seed voltage twice. The bitlines may be divided into one or more segments.

Abstract: An integrated circuit is provided. The integrated circuit includes a substrate and at least one dielectric layer and a metal layer formed upon the substrate. The at least one dielectric layer includes a terminal dielectric layer. The integrated circuit further includes a planar passivating layer formed upon the terminal dielectric layer.

Abstract: An integrated circuit is provided. The integrated circuit includes a substrate and at least one dielectric layer and a metal layer formed upon the substrate. The at least one dielectric layer includes a terminal dielectric layer. The integrated circuit further includes a planar passivating layer formed upon the terminal dielectric layer.

Abstract: The present invention provides in one embodiment thereof an integrated circuit (IC) that includes silicon substrate. The integrated circuit includes a plurality of dielectric and metal layers formed upon the silicon substrate. The plurality of dielectric and metal layers form a die active area. The metal have formed therein a first guard wall surrounding the die active area. The metal layers further have formed therein a second segmented guard wall. The segmented guard wall surrounds and staples the plurality of metal layers. The IC also includes a passivation layer adhering to the first and the segmented guard walls.

Abstract: A reference scheme for verifying the erasing and programming in an electrically erasable and electrically programmable read-only memory fabricated on a silicon substrate which employs a plurality of memory cells, each of which contains a floating gate. The reference scheme employs trimmable single cell reference devices for both the erase verify and program verify operations. The threshold voltages of the reference cells are trimmed to a level below (in the case of the erase verify reference cell) or above (in the case of the program verify reference cell) which all memory cells in the array will be considered in a particular program state (i.e., erased or programmed). In the case of the read reference device, a double-cell read referencing device combining the erase and program verify reference cells is described. Although, the double-cell referencing device is preferred, a trimmable read reference device is also taught.

Abstract: A semiconductor memory having a memory cell for storing a bit of data and a pull-down transistor for coupling the source of the memory cell to ground in order to read the memory cell. The pull-down transistor is comprised of a polysilicon gate coupled to a control means for switching the transistor ON/OFF; a drain diffusion region coupled to the source of the memory cell; and a source diffusion region coupled to ground. The source diffusion region is physically located closer to the memory cell than the drain diffusion region. Two P.sup.+ substrate taps are implemented--one on each side of the pull-down transistor. An N.sup.+ diffusion bar is coupled to V.sub.SS. The N.sup.+ diffusion bar and the adjacent P.sup.+ substrate tap are interleaved in a row and are coupled to metal layers by vias and contacts.

Abstract: A single polysilicon layer electrically programmable and electrically erasable read only memory cell is described. The cell utilizes an n-well inversion capacitor, formed in a semiconductor substrate as the control gate. One plate of the capacitor is formed from the same polysilicon layer as the floating gate of the memory device, thus capacitively coupling the floating gate and the inversion capacitor control gate. Additional erase performance is achieved by addition of a dedicated erase capacitor to the basic cell. Still further improvement in programming performance and protection against over-erase failure in a flash type EEPROM device is achieved by the addition of a select transistor. Prevention of program disturb and DC erase is also described.