Abstract: An arbitrator governs an arbitration between different power domains and sequences powering up the different power domains supplied by the same voltage supply (VS) circuit on the Chip. The arbitrator has sequencing logic that limits how many different power domains simultaneously power up to a maximum amount, which is less than enough instantaneous electrical current drawn on the VS-circuit to cause a reduction below a minimum allowable supply voltage level for the VS-circuit. The sequencing logic manages the sequencing of powering up the different power domains by factoring in i) whether different power domains arbitrating to power up are part of a set of power domains that share the VS-circuit, ii) an amount of an instantaneous electrical current drawn, and iii) an amount of credits available before the minimum allowable supply voltage level occurs for that VS-circuit. The sequencing logic controls a behavior of the power domains when powering up from multiple different behaviors.

Abstract: Data payload is passed over a boundary from a sender module (SM) on one side of the boundary to a receiver module (RM) on the other side of the boundary. The SM has two or more multiplexers to pass the data payload over to a receiver storage register in the RM. Each multiplexer has 1) its own read address pointer lane coming from sequencing logic located on the RM side and 2) data slots to send data payload from that multiplexer across the boundary to the receiver storage register in the RM in a qualified event synchronization. The sequencing logic ensures that the multiple read address pointers going to the multiplexers have a fixed alternating relationship amongst themselves; and thus, the multiple read address pointers syncopate between each other to move the data payload across the boundary to provide 100% throughput.

Abstract: An arbitrator governs an arbitration between different power domains and sequences powering up the different power domains supplied by the same voltage supply (VS) circuit on the Chip. The arbitrator has sequencing logic that limits how many different power domains simultaneously power up to a maximum amount, which is less than enough instantaneous electrical current drawn on the VS-circuit to cause a reduction below a minimum allowable supply voltage level for the VS-circuit. The sequencing logic manages the sequencing of powering up the different power domains by factoring in i) whether different power domains arbitrating to power up are part of a set of power domains that share the VS-circuit, ii) an amount of an instantaneous electrical current drawn, and iii) an amount of credits available before the minimum allowable supply voltage level occurs for that VS-circuit. The sequencing logic controls a behavior of the power domains when powering up from multiple different behaviors.

Abstract: Data payload is passed over a boundary from a sender module (SM) on one side of the boundary to a receiver module (RM) on the other side of the boundary. The SM has two or more multiplexers to pass the data payload over to a receiver storage register in the RM. Each multiplexer has 1) its own read address pointer lane coming from sequencing logic located on the RM side and 2) data slots to send data payload from that multiplexer across the boundary to the receiver storage register in the RM in a qualified event synchronization. The sequencing logic ensures that the multiple read address pointers going to the multiplexers have a fixed alternating relationship amongst themselves; and thus, the multiple read address pointers syncopate between each other to move the data payload across the boundary to provide 100% throughput.

Abstract: The present invention embodiment comprises an arrangement of integrated circuits with a UART device that is configurable to operate in a power-reduced mode while the clock frequency of serial data communication remains constant. In one example embodiment, an arrangement of a plurality of integrated circuit devices includes a first integrated circuit device driven by a first clock signal at a first clock rate. The arrangement contains a parallel data bus coupled to communicate with the first integrated circuit device in response to the first clock signal. The arrangement also includes a universal asynchronous receiver/transmitter (UART) chip with a serial communication circuit adapted to communicate serial data at a second rate defined by a second clock signal. The UART chip also encompasses a parallel bus interface circuit responsive to the first clock signal and adapted to pass data between the parallel data bus and the serial communication circuit.

Abstract: A circuit arrangement improves CPU efficiency by processing data through a FIFO circuit of a UART chip using a CPU adapted to detect, and respond with various options to, the current storage capacity of the FIFO circuit. In one example embodiment, a circuit arrangement includes a universal asynchronous receiver/transmitter (UART) chip having a FIFO circuit and an arithmetic logic unit (ALU) adapted to generate an N-bit variable binary signal, wherein the binary signal varies as a function of a current storage capacity of the FIFO circuit. The circuit arrangement further includes a control circuit communicatively coupled with the UART chip that is adapted to read the N-bit variable binary signal and, in response, to control the data flow through the FIFO circuit.

Abstract: A configurable universal asynchronous receiver/transmitter (UART) facilitates efforts to upgrade UART functionality in the field and replace older UART devices. In one example embodiment, an integrated circuit includes a universal asynchronous receiver/transmitter configured and arranged to operate in one of a plurality of modes, with each mode being selectable in response to mode-selecting data. The integrated circuit device includes an interface circuit electrically connected to the universal asynchronous receiver/transmitter and adapted to present the mode-selecting data to the universal asynchronous receiver/transmitter. The integrated circuit device also includes a selection circuit adapted to enable the mode-selecting data to pass from the interface circuit to the universal asynchronous receiver/transmitter.

Abstract: An integrated circuit arrangement is reconfigurable in the field to operate in one of a plurality of modes, including a test mode, in response to mode-selecting codes presented via a temporary register in the circuit. In one example embodiment, an arrangement of integrated circuits includes a reconfigurable integrated circuit configured and arranged to operate in one of a plurality of modes. The reconfigurable integrated circuit includes a register adapted to store data for temporary use, with each operating mode of the reconfigurable circuit being selectable in response to mode-selecting data code. An interface circuit is electrically connected to the reconfigurable integrated circuit and is adapted to present the mode-selecting data code to the reconfigurable integrated circuit. A selection circuit is adapted to enable the interface circuit to pass mode-selecting data to the reconfigurable integrated circuit.

Abstract: A configurable universal asynchronous receiver/transmitter (UART) facilitates efforts to upgrade UART functionality in the field and replace older UART devices. In one example embodiment, an integrated circuit includes a universal asynchronous receiver/transmitter configured and arranged to operate in one of a plurality of modes, with each mode being selectable in response to mode-selecting data. The integrated circuit device includes an interface circuit electrically connected to the universal asynchronous receiver/transmitter and adapted to present the mode-selecting data to the universal asynchronous receiver/transmitter. The integrated circuit device also includes a selection circuit adapted to enable the mode-selecting data to pass from the interface circuit to the universal asynchronous receiver/transmitter.

Abstract: A circuit arrangement improves CPU efficiency by processing data through a FIFO circuit of a UART chip using a CPU adapted to detect, and respond with various options to, the current storage capacity of the FIFO circuit. In one example embodiment, a circuit arrangement includes a universal asynchronous receiver/transmitter (UART) chip having a FIFO circuit and an arithmetic logic unit (ALU) adapted to generate an N-bit variable binary signal, wherein the binary signal varies as a function of a current storage capacity of the FIFO circuit. The circuit arrangement further includes a control circuit communicatively coupled with the UART chip that is adapted to read the N-bit variable binary signal and, in response, to control the data flow through the FIFO circuit.

Abstract: The present invention embodiment comprises an arrangement of integrated circuits with a UART device that is configurable to operate in a power-reduced mode while the clock frequency of serial data communication remains constant. In one example embodiment, an arrangement of a plurality of integrated circuit devices includes a first integrated circuit device driven by a first clock signal at a first clock rate. The arrangement contains a parallel data bus coupled to communicate with the first integrated circuit device in response to the first clock signal. The arrangement also includes a universal asynchronous receiver/transmitter (UART) chip with a serial communication circuit adapted to communicate serial data at a second rate defined by a second clock signal. The UART chip also encompasses a parallel bus interface circuit responsive to the first clock signal and adapted to pass data between the parallel data bus and the serial communication circuit.

Abstract: An integrated circuit arrangement is reconfigurable in the field to operate in one of a plurality of modes, including a test mode, in response to mode-selecting codes presented via a temporary register in the circuit. In one example embodiment, an arrangement of integrated circuits includes a reconfigurable integrated circuit configured and arranged to operate in one of a plurality of modes. The reconfigurable integrated circuit includes a register adapted to store data for temporary use, with each operating mode of the reconfigurable circuit being selectable in response to mode-selecting data code. An interface circuit is electrically connected to the reconfigurable integrated circuit and is adapted to present the mode-selecting data code to the reconfigurable integrated circuit. A selection circuit is adapted to enable the interface circuit to pass mode-selecting data to the reconfigurable integrated circuit.

Abstract: A method and apparatus for framing data in digital transmission lines automatically recognizes a framing format. The apparatus preferably includes a frame alignment apparatus that can recognize any one of a number of predetermined framing formats created by framing information on an input signal. The frame alignment apparatus outputs an aligning signal to an output frame counter, which counts the data and framing information on the input signal and outputs a frame synchronization signal according to the framing format. The input signal is also coupled to an output apparatus that outputs the input signal at the clock rate of a terminating apparatus. The frame alignment apparatus preferably includes a plurality of pattern recognizers able to recognize at least one of the framing formats and a storage apparatus for storing counts of successive data and framing information that match a framing pattern. The counts are preferably used to identify the framing information on the input signal and the framing format.

Abstract: A method and apparatus for framing data in digital transmission lines automatically recognizes a framing format. The apparatus preferably includes a frame alignment apparatus that can recognize any one of a number of predetermined framing formats created by framing information on an input signal. The frame alignment apparatus outputs an aligning signal to an output frame counter, which counts the data and framing information on the input signal and outputs a frame synchronization signal according to the framing format. The input signal is also coupled to an output apparatus that outputs the input signal at the clock rate of a terminating apparatus. The frame alignment apparatus preferably includes a plurality of pattern recognizers able to recognize at least one of the framing formats and a storage apparatus for storing counts of successive data and framing information that match a framing pattern. The counts are preferably used to identify the flaming information on the input signal and the flaming format.