Patents by Inventor Neal Taylor Christensen

Neal Taylor Christensen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5819061
    Abstract: In a partitioned process environment, storage is reassigned by a shuffle of guest absolute address spaces which may be reassigned among partitions without restriction as to the position of the space to be reassigned relative to the position of the partition to which it is to be assigned. The reassignment is accomplished by adjusting the origin addresses by an adjustment value corresponding to the size of the address space of an additional memory area to be added to a selected partition. Furthermore, the size of the address space of the selected partition is increased by the same adjustment value. The system employs duplicated origin and limit arrays which are used to convert from a partition (guest) absolute address to a system (host) absolute address and uses duplicated configuration arrays by which the system absolute addresses are converted to physical memory addresses.
    Type: Grant
    Filed: July 25, 1994
    Date of Patent: October 6, 1998
    Assignee: International Business Machines Corporation
    Inventors: Steven Gardner Glassen, Robert Stanley Capowski, Neal Taylor Christensen, Thomas Oscar Curlee, III, Ronald Franklin Hill, Moon Ju Kim, Matthew Anthony Krygowski, Allen Herman Preston, David Emmett Stucki, Frederick J. Cox
  • Patent number: 3964054
    Abstract: A response priority circuit arrangement for determining the priority among simultaneous responses from different access-time levels L3 and L2 in a storage hierarchy to maintain nearly the same order among the simultaneous responses as the order of their storage access requests.The storage requests were put into an indexed slot in a hardware queue. The index of the assigned queue slot is sent to a basic storage module (BSM) part of the hierarchy which is selected by the storage address supplied by the processor making the storage request. The selected BSM will have the requested data either in its main memory part (L3) or in its high-speed buffer part (L2).The priority circuit arrangement has a separate group of AND gates for each hierarchy level L3 and L2. The groups are interlocked by a circuit which disables the L2 group if any AND gate is enabled in the L3 group. Only one AND gate can be enabled in both L3 and L2 groups.
    Type: Grant
    Filed: June 23, 1975
    Date of Patent: June 15, 1976
    Assignee: International Business Machines Corporation
    Inventors: Eugene Joseph Annunziata, Neal Taylor Christensen