Patents by Inventor Nebojsa Bjegovic

Nebojsa Bjegovic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Negotiation between multiple processing units for switch mitigation
    Patent number: 10162776
    Abstract: A method for maintaining data and clock line synchronization, which may include a clock line that may be driven high after a clock line falling edge to mitigate a clock error. Additionally, the clock error may be mitigated by maintaining a saturated state of a device. Furthermore, a register may be connected to a microcontroller and/or a graphical processing unit to negotiate control of a switch and a bus.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: December 25, 2018
    Assignee: Apple Inc.
    Inventors: Nebojsa Bjegovic, Vanessa Cristina Heppolette
  • Negotiation Between Multiple Processing Units for Switch Mitigation
    Publication number: 20160306760
    Abstract: A method for maintaining data and clock line synchronization, which may include a clock line that may be driven high after a clock line falling edge to mitigate a clock error. Additionally, the clock error may be mitigated by maintaining a saturated state of a device. Furthermore, a register may be connected to a microcontroller and/or a graphical processing unit to negotiate control of a switch and a bus.
    Type: Application
    Filed: June 29, 2016
    Publication date: October 20, 2016
    Inventors: Nebojsa Bjegovic, Vanessa Cristina Heppolette
  • Negotiation between multiple processing units for switch mitigation
    Patent number: 9405716
    Abstract: A method for maintaining data and clock line synchronization, which may include a clock line that may be driven high after a clock line falling edge to mitigate a clock error. Additionally, the clock error may be mitigated by maintaining a saturated state of a device. Furthermore, a register may be connected to a microcontroller and/or a graphical processing unit to negotiate control of a switch and a bus.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: August 2, 2016
    Assignee: Apple Inc.
    Inventors: Nebojsa Bjegovic, Vanessa Cristina Heppolette
  • Negotiation between multiple processing units for switch mitigation
    Patent number: 8356200
    Abstract: A method for maintaining data and clock line synchronization, which may include a clock line that may be driven high after a clock line falling edge to mitigate a clock error. Additionally, the clock error may be mitigated by maintaining a saturated state of a device. Furthermore, a register may be connected to a microcontroller and/or a graphical processing unit to negotiate control of a switch and a bus.
    Type: Grant
    Filed: September 26, 2008
    Date of Patent: January 15, 2013
    Assignee: Apple Inc.
    Inventors: Nebojsa Bjegovic, Vanessa Cristina Heppolette
  • NEGOTIATION BETWEEN MULTIPLE PROCESSING UNITS FOR SWITCH MITIGATION
    Publication number: 20100083023
    Abstract: A method for maintaining data and clock line synchronization, which may include a clock line that may be driven high after a clock line falling edge to mitigate a clock error. Additionally, the clock error may be mitigated by maintaining a saturated state of a device. Furthermore, a register may be connected to a microcontroller and/or a graphical processing unit to negotiate control of a switch and a bus.
    Type: Application
    Filed: September 26, 2008
    Publication date: April 1, 2010
    Applicant: Apple Inc.
    Inventors: Nebojsa Bjegovic, Vanessa Cristina Heppolette