Patents by Inventor Nebojsa Makljenovic
Nebojsa Makljenovic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9965342Abstract: A data processing apparatus is provided having a hierarchy of layers comprising at least two data processing layers, each data processing layer configured to receive data and to generate processed data for passing to a next lower layer in said hierarchy, according to a protocol specific to that data processing layer. Each data processing layer is configured intermittently to add synchronization information to its processed data, the synchronization information providing semantic information required to interpret the processed data. Each data processing layer is further configured to output its synchronization information in response to a synchronization request signal received from a lower layer in said hierarchy, and at least one data processing layer is configured, when outputting its synchronization information, to issue its synchronization request signal to a higher layer in the hierarchy.Type: GrantFiled: March 16, 2010Date of Patent: May 8, 2018Assignee: ARM LimitedInventors: John Michael Horley, Nebojsa Makljenovic, Katherine Elizabeth Kneebone, Michael John Williams, Ian William Spray
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Patent number: 9953444Abstract: A graphics processing apparatus and method of performing graphics processing are provided. The graphics processing apparatus comprises a sequence of processing stages capable of performing graphics processing to generate a frame of display data. The graphics processing is performed on a tile-by-tile basis. The graphics processing apparatus is capable of determining if a current tile subject to the graphics processing is empty. At least one processing stage of the sequence of processing stages is omitted for graphics processing of the current tile in dependence on whether the current tile is empty.Type: GrantFiled: October 5, 2015Date of Patent: April 24, 2018Assignee: ARM LimitedInventors: Isidoros Sideris, Michel Patrick Gabriel Emil Iwaniec, Andrew Burdass, Nebojsa Makljenovic, Andreas Due Engh-Halstvedt
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Patent number: 9411662Abstract: A data processing apparatus comprises processing circuitry arranged to process processing threads using resources accessible to the processing circuitry. A pipeline is provided for handling at least two pending threads awaiting processing by the processing circuitry. The pipeline includes at least one resource-requesting pipeline stage for requesting access to resources for the pending threads. A priority controller controls priority levels of the pending threads. The priority levels define a priority with which pending threads are granted access to resources. When a pending thread reaches a final pipeline stage, if the request resources are not yet available then the priority level of that thread is raised selectively and the thread is returned to a first pipeline stage of the pipeline. If the requested resources are available then the thread is forwarded from the pipeline.Type: GrantFiled: July 16, 2013Date of Patent: August 9, 2016Assignee: ARM LimitedInventors: Nebojsa Makljenovic, Edvard Fielding, Andreas Due Engh-Halstvedt
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Publication number: 20160110837Abstract: A graphics processing apparatus and method of performing graphics processing are provided. The graphics processing apparatus comprises a sequence of processing stages capable of performing graphics processing to generate a frame of display data. The graphics processing is performed on a tile-by-tile basis. The graphics processing apparatus is capable of determining if a current tile subject to the graphics processing is empty. At least one processing stage of the sequence of processing stages is omitted for graphics processing of the current tile in dependence on whether the current tile is empty.Type: ApplicationFiled: October 5, 2015Publication date: April 21, 2016Inventors: Isidoros SIDERIS, Michel Patrick Gabriel Emil IWANIEC, Andrew BURDASS, Nebojsa MAKLJENOVIC, Andreas Due ENGH-HALSTVEDT
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Patent number: 8966494Abstract: A data processing apparatus has processing circuitry for processing threads using resources accessible to the processing circuitry. Thread handling circuitry handles pending threads which are waiting for resources required for processing. When a request is made for a resource which is not available, a lock is set to ensure that once the resource becomes available, the resource remains available until the lock is removed. This prevents other threads reallocating the resource. When a subsequent pending thread requests access to the same locked unavailable resource, the lock is transferred to that subsequent thread so that the latest thread accessing that resource is considered the lock owning thread. The lock is removed once the lock owning thread is ready for processing.Type: GrantFiled: March 16, 2012Date of Patent: February 24, 2015Assignee: ARM LimitedInventors: Nebojsa Makljenovic, Benjamin Charles James
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Patent number: 8589934Abstract: A data processing apparatus comprises processing circuitry arranged to process processing threads using resources accessible to the processing circuitry. A pipeline is provided for handling at least two pending threads awaiting processing by the processing circuitry. The pipeline includes at least one resource-requesting pipeline stage for requesting access to resources for the pending threads. A priority controller controls priority levels of the pending threads. The priority levels define a priority with which pending threads are granted access to resources. When a pending thread reaches a final pipeline stage, if the request resources are not yet available then the priority level of that thread is raised selectively and the thread is returned to a first pipeline stage of the pipeline. If the requested resources are available then the thread is forwarded from the pipeline.Type: GrantFiled: April 1, 2011Date of Patent: November 19, 2013Assignee: ARM LimitedInventors: Nebojsa Makljenovic, Edvard Fielding, Andreas Engh-Halstvedt
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Publication number: 20130305255Abstract: A data processing apparatus comprises processing circuitry arranged to process processing threads using resources accessible to the processing circuitry. A pipeline is provided for handling at least two pending threads awaiting processing by the processing circuitry. The pipeline includes at least one resource-requesting pipeline stage for requesting access to resources for the pending threads. A priority controller controls priority levels of the pending threads. The priority levels define a priority with which pending threads are granted access to resources. When a pending thread reaches a final pipeline stage, if the request resources are not yet available then the priority level of that thread is raised selectively and the thread is returned to a first pipeline stage of the pipeline. If the requested resources are available then the thread is forwarded from the pipeline.Type: ApplicationFiled: July 16, 2013Publication date: November 14, 2013Applicant: ARM LimitedInventors: Nebojsa MAKLJENOVIC, Edvard FIELDING, Andreas Due ENGH-HALSTVEDT
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Publication number: 20130247060Abstract: A data processing apparatus has processing circuitry for processing threads using resources accessible to the processing circuitry. Thread handling circuitry handles pending threads which are waiting for resources required for processing. When a request is made for a resource which is not available, a lock is set to ensure that once the resource becomes available, the resource remains available until the lock is removed. This prevents other threads reallocating the resource. When a subsequent pending thread requests access to the same locked unavailable resource, the lock is transferred to that subsequent thread so that the latest thread accessing that resource is considered the lock owning thread. The lock is removed once the lock owning thread is ready for processing.Type: ApplicationFiled: March 16, 2012Publication date: September 19, 2013Applicant: ARM LIMITEDInventors: Nebojsa MAKLJENOVIC, Benjamin Charles JAMES
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Publication number: 20120254882Abstract: A data processing apparatus comprises processing circuitry arranged to process processing threads using resources accessible to the processing circuitry. A pipeline is provided for handling at least two pending threads awaiting processing by the processing circuitry. The pipeline includes at least one resource-requesting pipeline stage for requesting access to resources for the pending threads. A priority controller controls priority levels of the pending threads. The priority levels define a priority with which pending threads are granted access to resources. When a pending thread reaches a final pipeline stage, if the request resources are not yet available then the priority level of that thread is raised selectively and the thread is returned to a first pipeline stage of the pipeline. If the requested resources are available then the thread is forwarded from the pipeline.Type: ApplicationFiled: April 1, 2011Publication date: October 4, 2012Applicant: ARM LIMITEDInventors: Nebojsa Makljenovic, Edvard Fielding, Andreas Due Engh-Halstvedt
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Publication number: 20110231691Abstract: A data processing apparatus is provided having a hierarchy of layers comprising at least two data processing layers, each data processing layer configured to receive data and to generate processed data for passing to a next lower layer in said hierarchy, according to a protocol specific to that data processing layer. Each data processing layer is configured intermittently to add synchronization information to its processed data, the synchronization information providing semantic information required to interpret the processed data. Each data processing layer is further configured to output its synchronization information in response to a synchronization request signal received from a lower layer in said hierarchy, and at least one data processing layer is configured, when outputting its synchronization information, to issue its synchronization request signal to a higher layer in the hierarchy.Type: ApplicationFiled: March 16, 2010Publication date: September 22, 2011Applicant: ARM LimitedInventors: John Michael Horley, Nebojsa Makljenovic, Katherine Elizabeth Kneebone, Michael John Williams, Ian William Spray