Abstract: A method of using a fet level simulator to check for races in a digital design. The method comprises varying digital design models input into the simulator. Each model comprises a clock gater circuit producing clocks with differing overlaps and dead times. Raw data files corresponding to each model input are generated by the fet level simulator. The raw data files preferably comprise lists of node values with corresponding time stamps. Corresponding latch node values in the raw data files are compared to identify the nodes of a circuit which are affected by races. Identifying affected latch nodes allows a race's root cause to be quickly pinpointed. Vector inputs to the fet level simulator may be varied. If vector inputs are varied, comparison of the raw data files comprises comparing the files generated for differing models with common vector inputs. Apparatus for implementing the above method is also disclosed.