Patents by Inventor Neelam AGARWAL

Neelam AGARWAL has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Superjunction transistor with implantation barrier at the bottom of a trench
    Patent number: 9048115
    Abstract: A method for fabricating a semiconductor device is provided. An epitaxial layer is grown on a substrate, wherein the epitaxial layer and the substrate have a first conductivity type. A trench is formed in the epitaxial layer. A barrier region is formed at a bottom of the trench. A doped region of a second conductivity type is formed in the epitaxial layer and surrounds sidewalls of the trench, wherein the barrier region prevents a dopant used for forming the doped region from reaching the epitaxial layer under the barrier region. The trench is filled with a dielectric material. A pair of polysilicon gates is formed on the epitaxial layer and on both sides of the trench.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: June 2, 2015
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Tsung-Hsiung Lee, Shang-Hui Tu, Gene Sheu, Neelam Agarwal, Karuna Nidhi, Chia-Hao Lee, Rudy Octavius Sihombing
  • SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20140117436
    Abstract: A method for fabricating a semiconductor device is provided. An epitaxial layer is grown on a substrate, wherein the epitaxial layer and the substrate have a first conductivity type. A trench is formed in the epitaxial layer. A barrier region is formed at a bottom of the trench. A doped region of a second conductivity type is formed in the epitaxial layer and surrounds sidewalls of the trench, wherein the barrier region prevents a dopant used for forming the doped region from reaching the epitaxial layer under the barrier region. The trench is filled with a dielectric material. A pair of polysilicon gates is formed on the epitaxial layer and on both sides of the trench.
    Type: Application
    Filed: October 26, 2012
    Publication date: May 1, 2014
    Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Tsung-Hsiung LEE, Shang-Hui TU, Gene SHEU, Neelam AGARWAL, Karuna NIDHI, Chia-Hao LEE, Rudy Octavius SIHOMBING