Patents by Inventor Neena Garg

Neena Garg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7492008
    Abstract: A method for forming a semiconductor-on-insulator (SOI) substrate is described incorporating the steps of heating a substrate, implanting oxygen into a heated substrate, cooling the substrate, implanting into a cooled substrate and annealing. The steps of implanting may be at several energies to provide a plurality of depths and corresponding buried damaged regions. Prior to implanting, the step of cleaning the substrate surface and/or forming a patterned mask thereon may be performed. The invention overcomes the problem of raising the quality of buried oxide and its properties such as surface roughness, uniform thickness and breakdown voltage Vbd.
    Type: Grant
    Filed: July 22, 2004
    Date of Patent: February 17, 2009
    Assignee: International Business Machines Corporation
    Inventors: Stephen Richard Fox, Neena Garg, Kenneth John Giewont, Junedong Lee, Siegfried Lutz Maurer, Dan Moy, Maurice Heathcote Norcott, Devendra Kumar Sadana
  • Patent number: 6967376
    Abstract: A method of fabricating a silicon-on-insulator (SOI) having a superficial Si-containing layer that has a reduced number of tile and divot defects is provided. The method includes the steps of: implanting oxygen ions into a surface of a Si-containing substrate, the implanted oxygen ions having a concentration sufficient to form a buried oxide region during a subsequent annealing step; and annealing the substrate containing implanted oxygen ions under conditions wherein the implanted oxygen ions form a buried oxide region which electrically isolates a superficial Si-containing layer from a bottom Si-containing layer. Moreover, the annealing conditions employed are capable of reducing the number of tile or divot defects present in the superficial Si-containing layer so as to allow optical detection of any other defect that has a lower density than the tile or divot defect. The present invention also relates to the SOI substrate that is produced using the inventive method.
    Type: Grant
    Filed: April 26, 2004
    Date of Patent: November 22, 2005
    Assignee: International Business Machines Corporation
    Inventors: Stephen R. Fox, Neena Garg, Kenneth J. Giewont, Junedong Lee, Devendra K. Sadana
  • Publication number: 20050003626
    Abstract: A method for forming a semiconductor-on-insulator (SOI) substrate is described incorporating the steps of heating a substrate, implanting oxygen into a heated substrate, cooling the substrate, implanting into a cooled substrate and annealing. The steps of implanting may be at several energies to provide a plurality of depths and corresponding buried damaged regions. Prior to implanting, the step of cleaning the substrate surface and/or forming a patterned mask thereon may be performed. The invention overcomes the problem of raising the quality of buried oxide and its properties such as surface roughness, uniform thickness and breakdown voltage Vbd.
    Type: Application
    Filed: July 22, 2004
    Publication date: January 6, 2005
    Inventors: Stephen Fox, Neena Garg, Kenneth Giewont, Junedong Lee, Siegfried Maurer, Dan Moy, Maurice Norcott, Devendra Sadana
  • Publication number: 20040266129
    Abstract: Disclosed herein is a method of providing improved electrical isolation in a separation by ion implanted oxide (SIMOX) process of making an SOI wafer. The method includes implanting ions into a substrate in a base dose implant conducted at a first energy level, implanting ions into the substrate at a second energy level in a second implant while the substrate is held at room temperature, and annealing the substrate to cause the implanted ions to be redistributed throughout the buried oxide (BOX) layer of the SOI wafer.
    Type: Application
    Filed: June 27, 2003
    Publication date: December 30, 2004
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joel P. DeSouza, Harold J. Hovel, Junedong Lee, Siegfried L. Maurer, Devendra K. Sadana, Dominic Schepis, Ghavam Shahidi, Neena Garg
  • Publication number: 20040197940
    Abstract: A method of fabricating a silicon-on-insulator (SOI) having a superficial Si-containing layer that has a reduced number of tile and divot defects is provided. The method includes the steps of: implanting oxygen ions into a surface of a Si-containing substrate, the implanted oxygen ions having a concentration sufficient to form a buried oxide region during a subsequent annealing step; and annealing the substrate containing implanted oxygen ions under conditions wherein the implanted oxygen ions form a buried oxide region which electrically isolates a superficial Si-containing layer from a bottom Si-containing layer. Moreover, the annealing conditions employed are capable of reducing the number of tile or divot defects present in the superficial Si-containing layer so as to allow optical detection of any other defect that has a lower density than the tile or divot defect. The present invention also relates to the SOI substrate that is produced using the inventive method.
    Type: Application
    Filed: April 26, 2004
    Publication date: October 7, 2004
    Applicant: INTERNATIOAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen R. Fox, Neena Garg, Kenneth J. Giewont, Junedong Lee, Devendra K. Sadana
  • Patent number: 6784072
    Abstract: A method for forming a semiconductor-on-insulator (SOI) substrate is described incorporating the steps of heating a substrate, implanting oxygen into a heated substrate, cooling the substrate, implanting into a cooled substrate and annealing. The steps of implanting may be at several energies to provide a plurality of depths and corresponding buried damaged regions. Prior to implanting, the step of cleaning the substrate surface and/or forming a patterned mask thereon may be performed. The invention overcomes the problem of raising the quality of buried oxide and its properties such as surface roughness, uniform thickness and breakdown voltage Vbd.
    Type: Grant
    Filed: July 22, 2002
    Date of Patent: August 31, 2004
    Assignee: International Business Machines Corporation
    Inventors: Stephen Richard Fox, Neena Garg, Kenneth John Giewont, Junedong Lee, Siegfried Lutz Maurer, Dan Moy, Maurice Heathcote Norcott, Devendra Kumar Sadana
  • Publication number: 20040013886
    Abstract: A method for forming a semiconductor-on-insulator (SOI) substrate is described incorporating the steps of heating a substrate, implanting oxygen into a heated substrate, cooling the substrate, implanting into a cooled substrate and annealing. The steps of implanting may be at several energies to provide a plurality of depths and corresponding buried damaged regions. Prior to implanting, the step of cleaning the substrate surface and/or forming a patterned mask thereon may be performed. The invention overcomes the problem of raising the quality of buried oxide and its properties such as surface roughness, uniform thickness and breakdown voltage Vbd.
    Type: Application
    Filed: July 22, 2002
    Publication date: January 22, 2004
    Applicant: International Business Machines Corporation
    Inventors: Stephen Richard Fox, Neena Garg, Kenneth John Giewont, Junedong Lee, Siegfried Lutz Maurer, Dan Moy, Maurice Heathcote Norcott, Devendra Kumar Sadana
  • Patent number: 6531411
    Abstract: A method of improving surface morphology of a semiconductor substrate when using an SOI technique comprises providing a silicon ingot positioned on a support member, orientating the silicon ingot in relation to the support member, and a cutting device, and cutting the silicon ingot along about a (100) crystal plane of the silicon ingot, preferably using a wire saw. This then provides a silicon substrate having an initial surface defining a miscut angle which is less than about 0.15 degrees from the (100) crystal plane. The method then comprises processing the silicon substrate using SIMOX processing, which includes implanting oxygen atoms in the silicon substrate to form a buried oxide layer and annealing the silicon substrate to provide a final substrate surface. Finally, the method includes accepting the final substrate surface for further processing when the final substrate surface measures between 2-20 Å RMS using an atomic force microscopy technique.
    Type: Grant
    Filed: November 5, 2001
    Date of Patent: March 11, 2003
    Assignee: International Business Machines Corporation
    Inventors: Anthony G. Domenicucci, Neena Garg, Kenneth J. Giewont, Richard J. Murphy, Gerd Pfeiffer, Gregory D. Pomarico, Frank J. Schmidt, Jr., Terrance M. Tornatore
  • Patent number: 6531375
    Abstract: A novel method for forming substrate contact regions on a SOI substrate without requiring additional space, and in order to provide lower diffusion capacitance. The method utilizes known semiconductor processing techniques. This method for selectively modifying the BOX region of a SOI substrate involves first providing a silicon substrate. Then, ion implanting the base using SIMOX techniques (e.g. O2 implant) is accomplished. Next, the substrate is photopatterned to protect the modified BOX region. Then, further ion implanting using a “touch-up” O2 implant is accomplished, thereby resulting in a good quality BOX as typically practiced. The final step is annealing the substrate. The area of the substrate, which had a mask present, would not receive the “touch-up” O2 implant (second ion implant), which in turn would result in a leaky BOX.
    Type: Grant
    Filed: September 18, 2001
    Date of Patent: March 11, 2003
    Assignee: International Business Machines Corporation
    Inventors: Kenneth J. Giewont, Eric Adler, Neena Garg, Michael J. Hargrove, Charles W. Koburger, III, Junedong Lee, Dominic J. Schepis, Isabel Ying Yang
  • Publication number: 20020190318
    Abstract: A method of fabricating a silicon-on-insulator (SOI) having a superficial Si-containing layer that has a reduced number of tile and divot defects is provided. The method includes the steps of: implanting oxygen ions into a surface of a Si-containing substrate, the implanted oxygen ions having a concentration sufficient to form a buried oxide region during a subsequent annealing step; and annealing the substrate containing implanted oxygen ions under conditions wherein the implanted oxygen ions form a buried oxide region which electrically isolates a superficial Si-containing layer from a bottom Si-containing layer. Moreover, the annealing conditions employed are capable of reducing the number of tile or divot defects present in the superficial Si-containing layer so as to allow optical detection of any other defect that has a lower density than the tile or divot defect. The present invention also relates to the SOI substrate that is produced using the inventive method.
    Type: Application
    Filed: June 19, 2001
    Publication date: December 19, 2002
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen R. Fox, Neena Garg, Kenneth J. Giewont, Junedong Lee, Siegfried L. Maurer, Maurice H. Norcott, Devendra K. Sadana
  • Patent number: 6495429
    Abstract: A method to control the quality of a buried oxide region, and to substantially reduce or eliminate deep divots in SOI substrates is provided. Specifically, the inventive method includes the steps of implanting oxygen ions into a surface of a Si-containing substrate; and annealing the Si-containing substrate containing the implanted oxygen ion at a temperature of about 1300° C. or above and in a chlorine-containing ambient so as to form a buried oxide region that electrically isolates a superficial Si-containing layer from a bottom Si-containing layer. The chlorine-containing ambient employed in the annealing step includes oxygen and a chlorine-containing carrier gas such as HCl, methylene chloride, trichloroethylene and trans 1,2-dichloroethane.
    Type: Grant
    Filed: January 23, 2002
    Date of Patent: December 17, 2002
    Assignee: International Business Machines Corporation
    Inventors: Michael E. Adamcek, Anthony G. Domenicucci, Stephen R. Fox, Neena Garg, Kenneth J. Giewont, Thomas R. Kupiec, Junedong Lee, Devendra K. Sadana
  • Patent number: 6488778
    Abstract: An apparatus and method for controlling wafer temperature and environment is provided. The apparatus includes a batch processing fixture for batch processing wafers at a first elevated temperature. The batch of wafers is not substantially ramped in temperature within the batch processing fixture. The apparatus also includes a single wafer processing apparatus for rapidly ramping temperature of a wafer of the batch from the first elevated temperature wherein a uniform temperature across the wafer is maintained during the ramping. Another embodiment of the apparatus (10) includes an RTP chamber (20) having an inert or reducing environment and that includes a pedestal (24) for holding a single wafer (16) and a heater unit (22) arranged so as to uniformly and rapidly heat the single wafer.
    Type: Grant
    Filed: March 16, 2000
    Date of Patent: December 3, 2002
    Assignee: International Business Machines Corporation
    Inventors: Arne W. Ballantine, Peter A. Emmi, Walter J. Frey, Michael J. Gambero, Neena Garg, Byeongju Park, Donald L. Wilson