Patents by Inventor Neeraj Bhardwaj

Neeraj Bhardwaj has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11961220
    Abstract: Apparatuses and methods are disclosed for handling integrated circuits in automated testing. The handler apparatus includes an upper assembly that is selectively translatable above a testing surface and a lower bracket extending from and positioned below the upper assembly. The lower bracket forms a first opening, is selectively moveable upward and downward, and includes a rotatable finger extending downward to pick up and place an integrated circuit in a socket. The handier may further include an image sensor to detect potential error conditions, and a tool extending from the lower bracket to open and close a lid on the socket. The methods include sensing an image of an integrated circuit during certain phases of testing, analyzing the image to determine if the integrated circuit is positioned correctly, and correcting any detected error conditions before continuing with the automated testing.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: April 16, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Neeraj Bhardwaj, Neha Vernekar, Janardhan Venkata Raju, Shubham Mehrotra, Arun Adoni, Mahit Arun Warhadpande, Shimee Gupta, Goda Devi Addanki, Pavinkumar Ramasamy, Binoy Jose Maliakal
  • Patent number: 11454665
    Abstract: A nontransitory computer-readable program storage medium storing program instructions. The program, when executed by a processor, has the processor capable of receiving a set of input data, the input data relating to devices on a test board for testing a device under test. The program, when executed by a processor, also is capable of transforming the set of input data into test board mapping data. The test board mapping data comprises an ordered listing of potential test points along a path that couples to a conductive surface, wherein the potential test points are derived from at least one of the test board attributes. Further, the program, when executed by a processor, is capable of identifying a selected test point from among the one or more potential test points, the selected test point for spike check probing of the device under test.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: September 27, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: William Joshua Bush, Neeraj Bhardwaj, Erfan Shirazian, Madhusudan Sampath, Pavinkumar Ramasamy
  • Publication number: 20200033403
    Abstract: Apparatus for cooperating with a stationary integrated circuit test board. The apparatus includes a frame for positioning relative to a stationary integrated circuit test board, where the test board is for coupling to an integrated circuit device under test. The apparatus also includes a probe having a tip, and a processor-controlled actuator apparatus coupled to the frame and for moving the probe tip to selectively electrically contact a test point on the integrated circuit test board.
    Type: Application
    Filed: July 26, 2019
    Publication date: January 30, 2020
    Inventors: William Joshua Bush, Neeraj Bhardwaj, Erfan Shirazian, Madhusudan Sampath, James Scott Mason, Yazdi Contractor, Pavinkumar Ramasamy
  • Publication number: 20200033397
    Abstract: A nontransitory computer-readable program storage medium storing program instructions. The program, when executed by a processor, has the processor capable of receiving a set of input data, the input data relating to devices on a test board for testing a device under test. The program, when executed by a processor, also is capable of transforming the set of input data into test board mapping data. The test board mapping data comprises an ordered listing of potential test points along a path that couples to a conductive surface, wherein the potential test points are derived from at least one of the test board attributes. Further, the program, when executed by a processor, is capable of identifying a selected test point from among the one or more potential test points, the selected test point for spike check probing of the device under test.
    Type: Application
    Filed: July 26, 2019
    Publication date: January 30, 2020
    Inventors: William Joshua Bush, Neeraj Bhardwaj, Erfan Shirazian, Madhusudan Sampath, Pavinkumar Ramasamy
  • Publication number: 20190227117
    Abstract: Apparatuses and methods are disclosed for handling integrated circuits in automated testing. The handler apparatus includes an upper assembly that is selectively translatable above a testing surface and a lower bracket extending from and positioned below the upper assembly. The lower bracket forms a first opening, is selectively moveable upward and downward, and includes a rotatable finger extending downward to pick up and place an integrated circuit in a socket. The handier may further include an image sensor to detect potential error conditions, and a tool extending from the lower bracket to open and dose a lid on the socket. The methods include sensing an image of an integrated circuit during certain phases of testing, analyzing the image to determine if the integrated circuit is positioned correctly, and correcting any detected error conditions before continuing with the automated testing.
    Type: Application
    Filed: March 19, 2018
    Publication date: July 25, 2019
    Inventors: Neeraj Bhardwaj, Neha Vernekar, Janardhan Venkata Raju, Shubham Mehrotra, Arun Adoni, Mahit Arun Warhadpande, Shimee Gupta, Goda Devi Addanki, Pavinkumar Ramasamy, Binoy Jose Maliakal
  • Patent number: D887540
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: June 16, 2020
    Assignee: Loto Labs, Inc.
    Inventors: Neeraj Bhardwaj, Matthew Greenfield, Peter Nysen, Grant Bell, Anderson Martinez, Brandon Harsell, Abelardo Duran