Abstract: Various implementations described herein are directed to a method that identifies a memory instance with multiple tile-cells. The memory instance has memory instance leakage data, and each tile-cell of the multiple tile-cells has tile-cell leakage data. The method subdivides the multiple tile-cells into multiple categories based on a relationship between the memory instance leakage data and the tile-cell leakage data. The method obtains measured leakage data for each tile-cell of the multiple tile-cells by simulating the memory instance based on the memory instance leakage data and the tile-cell leakage data for each category of the multiple categories. The method determines a combined leakage of the memory instance by combining the measured leakage data for each tile-cell of the multiple tile-cells.

Abstract: Various implementations described herein are directed to a method that identifies a memory instance with multiple tile-cells. The memory instance has memory instance leakage data, and each tile-cell of the multiple tile-cells has tile-cell leakage data. The method subdivides the multiple tile-cells into multiple categories based on a relationship between the memory instance leakage data and the tile-cell leakage data. The method obtains measured leakage data for each tile-cell of the multiple tile-cells by simulating the memory instance based on the memory instance leakage data and the tile-cell leakage data for each category of the multiple categories. The method determines a combined leakage of the memory instance by combining the measured leakage data for each tile-cell of the multiple tile-cells.

Abstract: A silicon compiler, such as a memory compiler, provides for pin-based noise characterization in a computationally efficient manner. For a given user-provided option set, a silicon compiler provides a noise database for the set of all available memory instances by performing pin-based noise characterization on only a subset of the set of available memory instances.

Abstract: Various implementations described herein are directed to a computing device. The computing device may include a mapper module that receives a user configuration input of a destination corner for building a destination corner database. The mapper module may include a decision making engine that decides fabrication parameters for building the destination corner database based on the verified user configuration input and memory compiler metadata. The computing device may include a builder module that performs a simulation of the destination corner based on the fabrication parameters, collects simulation results data associated with the simulation, and builds the destination corner database for the destination corner based on the simulation results data and source corner data.

Abstract: Various implementations described herein are directed to a computing device. The computing device may include a mapper module that receives a user configuration input of a destination corner for building a destination corner database. The mapper module may include a decision making engine that decides fabrication parameters for building the destination corner database based on the verified user configuration input and memory compiler metadata. The computing device may include a builder module that performs a simulation of the destination corner based on the fabrication parameters, collects simulation results data associated with the simulation, and builds the destination corner database for the destination corner based on the simulation results data and source corner data.

Abstract: A silicon compiler, such as a memory compiler, provides for pin-based noise characterization in a computationally efficient manner. For a given user-provided option set, a silicon compiler provides a noise database for the set of all available memory instances by performing pin-based noise characterization on only a subset of the set of available memory instances.

Abstract: An approach for reducing antenna effects in integrated circuits involves evaluating an integrated circuit design to identify one or more problem interconnects that satisfy certain antenna effect criteria. The problem interconnects are selectively connected to one or more discharge paths and the integrated circuit design is updated to reflect the connections to the one or more discharge paths.