Abstract: A networking application processor is provided. The processor includes an input socket configured to receive data packets. The processor includes a memory for holding instructions and circuitry configured to access data structures associated with the processing stages. The circuitry configured to access data structures enables a single cycle access to an operand from a memory location. An arithmetic logic unit (ALU) is provided. Circuitry for aligning operands to be processed by the ALU is included. The circuitry for aligning the operands causes the operand to be aligned by a lowest significant bit, wherein the circuitry for aligning the operand supplies an extension to the operand to allow the ALU to process different size operands.

Abstract: A hardware-implemented video broadcasting receiver is described that is capable handling back-to-back and parallel time slices in an efficient manner, thereby providing improved receiver performance. In one implementation, the hardware-implemented video broadcasting receiver is capable of handling back-to-back time slices of up to 2 Megabits (Mbits) each and, depending upon the MPE-FEC frame size associated with each time slice, up to 8 parallel time slices or up to 4 parallel time slices transmitted back-to-back with 4 other parallel time slices. The hardware-implemented video broadcasting receiver advantageously permits more efficient and flexible use of the available spectrum and increases interoperability with other DVB-H compliant equipment.

Abstract: A system and method for improved performance by a DVB-H receiver is described that allows good Internet Protocol (IP) packets in a Multiprotocol Encapsulation-Forward Error Correction (MPE-FEC) frame to be salvaged even when there are other IP packets in the frame that may have bytes in error after the performance of MPE-FEC operations. To achieve this, the system and method provides a means for ascertaining where IP packets loaded into a memory begin and end in a manner that can be relied upon even when individual bytes of the IP packets, such as certain bytes of the IP packet header used to determine total packet length, may be in error.

Abstract: A hardware-implemented video broadcasting receiver is described. The hardware-implemented video broadcasting receiver includes a radio frequency (RF) tuner, a demodulator connected to the RF tuner, link layer logic connected to the demodulator, and a power manager connected to the RF tuner, the demodulator and the link layer logic. The power manager is configured to receive delta-T values extracted from a transport stream by the link layer logic, to determine whether each of the RF tuner, the demodulator and the link layer logic can be powered down based on the delta-T values, and to power down the RF tuner, the demodulator and the link layer logic based on the determination, thereby reducing the average power consumed by the video broadcasting receiver.

Abstract: A method for transparently presenting different size operands to be processed is provided. The method initiates with providing a first operand having a first bit-width. Then, a bit width of a second operand associated with a processor is determined. The second operand has a greater bit width than the first operand. Next, the first operand is transformed by aligning a least significant bit of the first operand to a lowest bit position of a transformed operand having a bit size equal to the second operand. Then, the bits of the transformed operand are sign extended and padded in a manner to allow carry propagation. Next, the transformed operand is transmitted to the processor. A method for shifting operands and a processor are also provided.

Abstract: A networking application processor is provided. The processor includes an input socket configured to receive data packets. The processor includes a memory for holding instructions and circuitry configured to access data structures associated with the processing stages. The circuitry configured to access data structures enables a single cycle access to an operand from a memory location. An arithmetic logic unit (ALU) is provided. Circuitry for aligning operands to be processed by the ALU is included. The circuitry for aligning the operands causes the operand to be aligned by a lowest significant bit, wherein the circuitry for aligning the operand supplies an extension to the operand to allow the ALU to process different size operands.

Abstract: A method for transparently presenting different size operands to be processed is provided. The method initiates with providing a first operand having a first bit-width. Then, a bit width of a second operand associated with a processor is determined. The second operand has a greater bit width than the first operand. Next, the first operand is transformed by aligning a least significant bit of the first operand to a lowest bit position of a transformed operand having a bit size equal to the second operand. Then, the bits of the transformed operand are sign extended and padded in a manner to allow carry propagation. Next, the transformed operand is transmitted to the processor. A method for shifting operands and a processor are also provided.